Figure 5-20 to Fig. 5-23 show the reverse and forward current-voltage characteristics of different temperature for different contact-hole processes. All the reverse characteristics for different contact-hole process showed voltage dependent at low temperature and voltage independent at high temperature. According to the reverse current equation:
kT
At low temperature, Igen dominates reverses reverse current and at high temperature, Idiff
dominates reverse current. All four samples showed good electrical characteristics. Figure 5-24 shows the Arrhenius plot. From the plot of ln(IR/T3) versus 1/kT, the slop gives the effective energy gap. The calculated energy gaps are shown in Table 5-1. The energy gap at high temperature (>130℃) was about twice the energy gap at low temperature (<130℃).
These results matched the prediction of reverse current equation. For the samples of different contact-hole processes, however, the energy gap did not show obvious difference. The results again revealed the same phenomenon as for ideality factor. That was, the plasma damage may only affected the diode of the junction depth less than 1000Å.
5.5SUMMARY
The optimum process condition of ultra-shallow junction n+/p diode with nickel silicide has been found out in work. It was found that the leakage current increases with the
silicide.
The new S_LPD process for contact-hole formation was also developed in this study.
This technology was performed under a non-plasma environment. From the experimental results, S_LPD technology showed the lowest ideality factor and highest barrier height for Schottky diode. On the contrary, TEOS_RIE with the PECVD oxide deposition and RIE etching showed the poorest characteristics. For the ultra-shallow junction n+/p diode, the electrical characteristics including current-voltage curve, ideality factor and effective energy gap did not show obvious difference. From the results of Schottky diode and n+/p diode, it was suggested that the plasma damage may influence the junction depth between 500Å to 1000Å. This indicated that the sub-100nm device with the junction depth below 1000Å may be affected by the plasma damage including PECVD, RIE and so on. According to above mentioned, it is believed the S_LPD technology will be the promising technology for future advanced device fabrication.
TABLE 5-1
Summary of Device Parameters for Different Contact-Hole Processes S_LPD LPD_RIE TEOS_RIE TEOS_BOE Schottky Diode
Ideality Factor η (0.1 - 0.2V)
1000×1000 µm2 1.24 1.33 1.38 1.37
500×500 µm2 1.20 1.26 1.31 1.29
200×200 µm2 1.11 1.15 1.16 1.17
Barrier Height ΦBn (0.1V)
1000×1000 µm2 (V) 0.61 0.55 0.50 0.51
n+/p Diode
JRA 5.40×10-8 6.09×10-8 3.49×10-8 4.01×10-8 JRP 3.86×10-9 8.01×10-9 1.36×10-10 4.08×10-10
Ideality Factor η (0.1 - 0.3V)
1000×1000 µm2 1.11 1.13 1.09 1.12
Energy Gap Eg (1V)
<130℃ (eV) 0.73 0.68 0.72 0.62
>130℃ (eV) 1.11 1.09 1.18 1.06
TABLE 5-2
Summary of Diode I-V Parameters with Different Nickel Thickness
Nickel
Thickness IF (A) IR (A) JRA (A/cm2) JRP (A/cm) 100Å 9.93×10-8 7.34×10-12 3.59×10-10 9.39×10-12 150Å 1.08×10-7 2.17×10-10 1.28×10-8 2.22×10-10 200Å 1.33×10-7 3.37×10-10 5.10×10-9 7.15×10-10
TABLE 5-3
Summary of Diode I-V Parameters with Different Silicide Formation Temperature
RTA
Temperature IF (A) IR (A) JRA (A/cm2) JRP (A/cm) 400℃ 2.90×10-7 1.90×10-9 -1.01×10-7 7.29×10-9 450℃ 2.64×10-7 1.20×10-9 -4.90×10-8 4.23×10-9 500℃ 1.33×10-7 3.37×10-10 5.10×10-9 7.15×10-10 550℃ 1.34×10-7 1.40×10-10 5.70×10-9 2.07×10-10 600℃ 1.01×10-7 1.76×10-11 3.40×10-10 3.54×10-11 650℃ 1.14×10-7 1.41×10-11 1.87×10-10 3.05×10-11
Refrigerated Circulator LPD Solution
Sample Wafer Circular Water
at Permanent Temperature Immersion
Solution Tank
Fig. 5-1. The schematic diagram of LPD apparatus.
0 0.01 0.02 0.03 0.04
20 30 40 50 60
Blanket Deposition
Selective Deposition
No Deposition
Deposition Temperature ( C)o
Si(OH)4 Concentration (mol/L)
Fig. 5-3. The process window of S_LPD.
Fig. 5-4. SEM photographs of (a) No deposition, (b) Selective deposition and (c) Blanket deposition.
LOCOS isolation
Nickel silicide
Lithography + LPD
1. LPD 2. PE-TEOS
P.R. remove + HF dip P.R. remove
Metallization Metallization
+ Lithography +1. RIE 2. BOE
(i) S_LPD (ii) LPD_RIE
(iii) TEOS_RIE (iv) TEOS_BOE
n+ Implant + RTA
Nickel silicide
Lithography + LPD
P.R. remove + HF dip P.R. remove
Metallization Metallization
1. LPD
2. PE-TEOS+ Lithography +1. RIE 2. BOE
(i) S_LPD (ii) LPD_RIE
(iii) TEOS_RIE (iv) TEOS_BOE
(a) (b)
Fig. 5-6. Process flow of ultra-shallow junction n+/p diodes with contact-hole prepared by (a) S_LPD and (b) LPD_RIE, TEOS_RIE, and TEOS_BOE.
0 2 4 6 8 10
-5 -4 -3 -2 -1 0 1 10-6
10-5 10-4 10-3 10-2 10-1
Current, I D (A)
Bias Voltage, VD (V) S_LPD
LPD_RIE TEOS_RIE TEOS_BOE Area = 1000 x 1000µm2
Fig. 5-8. The current-voltage characteristics of schottky diodes with different contact-hole processes.
1.0
2.50 2.75 3.00 3.25 3.50
Fig. 5-10. (a) Richardson plot and (b) Barrier height of different contact-hole processes.
0 500 1000 1500 2000 2500
1016 1017 1018 1019 1020 1021
97.5 nm 90 nm
Arsenic_10keV Arsenic_20keV Arsenic_30keV
75 nm
Concertration(Atoms/cm3 )
Depth (Angstrom)
Fig. 5-11. SIMS depth profiles with different ion implantation energy.
-1 0 1 2 3 4 5 10-12
10-10 10-8 10-6 10-4
10-2 Area = 1000x1000 µm2
RTA:500oC, 30s
Ni 15 nm
Ni 20 nm Ni 10 nm
Current, I D (A)
Bias Voltage, VD (V)
Fig. 5-12. I-V characteristics of n+/p ultra-shallow junction diodes with different nickel thickness.
1
Forward Current, V (A)
Cumulative Probability (%)
-1 0 1 2 3 4 5 10-12
10-10 10-8 10-6 10-4
10-2 Area = 1000x1000 µm2 Ni = 20 nm
400oC 450oC 500oC 550oC 600oC 650oC
Current, I D (A)
Bias Voltage, VD (V)
Fig. 5-14. I-V characteristics of n+/p ultra-shallow junction diodes with different silicide formation temperature.
1
-1 0 1 2 3 4 5 10-12
10-10 10-8 10-6 10-4 10-2
S-LPD LPD_RIE Current, I D (A)
Bias Voltage, VD (V)
TEOS_BOE TEOS_RIE
S_LPD LPD_RIE TEOS_RIE TEOS_BOE
Fig. 5-16. I-V characteristics of silicide ultra-shallow junction with different contact-hole processes.
1
0 300 600 900 10-8
10-7 10-6 10-5
J R (A/cm-2 )
P/A Ratio (cm-1)
S_LPD LPD_RIE TEOS_RIE TEOS_BOE
Fig. 5-18. The leakage current density of different peripheral length to area ratio.
0.9 1.0 1.1 1.2 1.3 1.4
TEOS_BOE TEOS_RIE
LPD_RIE
Ideality Factor
S_LPD
Measured @ V
F= 0.1~0.3V
Fig. 5-19. The ideality factor distribution of n+/p diodes for different contact-hole processes.
5 4 3 2 1 0
Reverse Current, I R (A)
Reverse Voltage, V
Forward Current, I F (A)
Forward Voltage, V
Fig. 5-20. The (a) Reverse and (b)Forward current-voltage characteristics of different temperature for S_LPD sample.
5 4 3 2 1 0
Reverse Current, I R (A)
Reverse Voltage, VR (V)
Forward Current, I F (A)
Forward Voltage, V (V)
230C
5 4 3 2 1 0
Reverse Current, I R (A)
Reverse Voltage, V
Forward Current, I F (A)
Forward Voltage, VF (V)
Fig. 5-22. The (a) Reverse and (b)Forward current-voltage characteristics of different temperature for TEOS_RIE sample.
5 4 3 2 1 0
Reverse Current, I R (A)
Reverse Voltage, V
Forward Current, I F (A)
Forward Voltage, V (V)
230C
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 -42
-40 -38 -36 -34 -32 -30 -28 -26
-24 S_LPD
LPD_RIE TEOS_RIE TEOS_BOE
ln(I R/T3 )
1000/T (K-1) Bias Voltage = 1V
Area = 1000 x 1000 µm2
Fig. 5-24. The Arrhenius plot of diodes for different contact-hole processes.
C
HAPTER6
Conclusions and Future Works
6.1CONCLUSIONS
In chapter 2, AMC in air and on the surfaces of wafers was quantitatively analyzed.
Air sampling results reveal that a CB with chemical filters can only effectively remove inorganic ions, while one further equipped with a PTFE main filter can eliminate not only organic contaminations but also boron and metal. A CB with a GF filter still has a high concentration of D6. Wafer sampling results also demonstrate that each filter can, indeed, reduce the metal concentration to a level that corresponds to no exposure to air. Wafers exposed under a PTFE filter have less organic contaminations than those in the CR, but a GF filter shows high contamination of silicon-based organic D6, because of the binder used in the GF filter. In summary, the results obtained by air and wafer sampling are highly consistent.
The effects of AMC on device performance were also investigated using a MOS capacitor.
The samples exposed in the CB under the PTFE filter have nearly the same leakage current density and breakdown field distribution as the BLANK sample, implying that the exposed wafers have few defects and exhibit slight degradation of film quality. However, the samples in the CB under a GF filter suffer an obviously degraded breakdown field, leakage current density, and Qbd because of high concentrations of organic compounds. All these results reveal that AMC will become an important issue in future nanodevice fabrication. An AMC-free
In chapter 3, the qualitative and quantitative analyses of AMC in the CB with different filter module in HF vapor environment were investigated. The experimental results showed that the GF ULPA filter will release boron and organic contaminants in HF vapor environment, while the PTFE ULPA filter still maintained low concentration of contaminants.
The effects of the materials from which air filters are made on device characteristics were also investigated. The glass-fiber ULPA filter released AMC when exposed in an HF vapor environment. These contaminants included organic compounds and boron trace dopants and degraded the device characteristics. In contrast, the HF vapor did not affect the PTFE ULPA filter. These results suggested that the PTFE fiber can be a good ULPA filter material for providing a very clean cleanroom environment.
In chapter 4, the sheet resistances of NiSi on different silicon substrates were investigated. It was found that the NiSi formed with 200Å-thick nickel was stable and showed low sheet resistance between 400 and 650 RTA℃ ℃ -1, and still stable after 700 RTA℃ -2 for 30s on c-Si and apoly-Si. In the same experiment, the NiSi on poly-Si showed low sheet resistance below 600 RTA℃ -1. After the SEM micrographs observation, the NiSi showed different surface morphology on poly-Si, a-Si, and apoly-Si. At the lower RTA temperature, the surface was uniform. As the dark spots or agglomeration appear with the increasing temperature, the sheet resistance of NiSi began to increase. At the higher RTA temperature, the micro-crack or agglomeration arose on the surface of NiSi on poly-Si and apoly-Si, which results in the higher sheet resistance. As for the research of the linewidth effects of NiSi sheet resistance on poly-Si, a-Si, and apoly-Si, it was found that the appearance of dark spots or agglomeration would affect the sheet resistance of NiSi seriously. For 600 RTA on poly℃ -Si and apoly-Si, the sheet resistances of NiSi increase. Even so, it is more obvious with the narrower linewidth. It was observed that the behavior of NiSi sheet resistance at 600 RTA ℃ on a-Si is similar to that on apoly-Si. This is due to the effect of dopant activation at 1000 ℃
for 30s RTA. Due to the linewidth effects, the process window of NiSi RTA temperature was ranging from 400 to 550 . In the last section of this chapter, the thermal stability of NiSi ℃ ℃ after the second RTA at the temperatures ranging from 500 to 800 for 30s ℃ ℃ was tested.
NiSi on a-Si showed the best thermal stability. But for NiSi on c-Si, Ni will continuously diffuse and cause the sheet resistance to increase. Compared to the columnar poly silicon (poly-Si), the non-columnar poly silicon (apoly-Si) is more stable in the same thermal treatment.
In chapter 5, the optimum process condition of ultra-shallow junction n+/p diode with nickel silicide has been found out in work. It was found that the leakage current increases with the increasing of nickel thickness. This phenomenon resulted from the approach of nickel silicide to junction depletion region. It was also found that the leakage current decreases with the increasing silicide formation temperature. This is due to the complete formation of nickel silicide. The new S_LPD process for contact-hole formation was also developed in this study. This technology was performed under a non-plasma environment.
From the experimental results, S_LPD technology showed the lowest ideality factor and highest barrier height for Schottky diode. On the contrary, TEOS_RIE with the PECVD oxide deposition and RIE etching showed the poorest characteristics. For the ultra-shallow junction n+/p diode, the electrical characteristics including current-voltage curve, ideality factor and effective energy gap did not show obvious difference. From the results of Schottky diode and n+/p diode, it was suggested that the plasma damage may influence the junction depth between 500Å to 1000Å. This indicated that the sub-100nm device with the junction depth below 1000Å may be affected by the plasma damage including PECVD, RIE and so on.
6.2SUGGESTIONS FOR FUTURE WORK
The effects of AMC and plasma process on the device performance have been studied.
These studies, however, mainly focused on the individual process step. As for the development of nano-device, these studies should be considered in the complete device fabrication. Suggestions for future work are list as follows:
(1) Full nano-device processes are suggested to use for the complete study of AMC on device characteristics.
(2) The reliability study of nano-device influenced by the AMC.
(3) Physical and chemical studies of the effect of plasma process to nano-device.
(4) The use of S_LPD technology to full nano-device fabrication and the reliability test for this improvement technology.
R
EFERENCES[1] MA. Rappa, “Future directions in controlling particle contamination in semiconductor integrated circuit manufacturing: an industry survey,” 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, New York, NY, USA, Nov.
14-16, 1994.
[2] International Technology Roadmap for Semiconductors (ITRS), Yield Enhancement, 2003 Edition.
[3] D. Kinkead, M. Joffe, J. Higley, O. Kishkovich, “Forecast of Airborne Molecular Contamination Limits for the 0.25 Micron High Performance Logic Process,” Technology Transfer # 95052812A-TR SEMATECH, May 31, 1995.
[4] M. Inoue, T. Noda, M. Togawa, H. Inaba, H. Gomi, T. Yoshida, T. Okada, “Study on Boron Contamination in Clean Room,” 12th International Symposium on Contamination Control, Yokohama, Japan, 1994.
[5] H. Yoshino, T. Itani, M. Takimoto, and H. Tanabe, “Photoacid Structure Effects on Environmental Stability of 193-nm Chemically Amplified Positive Resists,”
Microprocesses and Nanotechnology Conference, Digest of paper International, p.76, 1999.
[6] T. Morimoto, T. Ohguro, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, I. Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, and H. Iwai, “Self-Aligned Nickel-Mono-Silicide Technology for High-Speed Deep Submicrometer Logic CMOS ULSI,” IEEE Transactions on electron devices, vol. 42, No. 5, pp.915-922, May 1995.
[7] R. Mukai, S. Ozawa, H. Yagi, “Compatibility of NiSi in the self-aligned silicide process for deep submicrometer devices,” Thin Solid Films, 270, pp.567-572, 1955.
[8] L. M. Ephrath, “REACTIVE ION ETCHING FOR VLSI,” IEDM, pp.402- 404, 1980.
[9] K. Tani, T. Yamaji and S. Nishikawa, “Effect of Contact-Hole-Etching Damage on Aluminum Chemical Vapor Deposition,” Jpn. J. Appl. Phys., Vol. 31, pp.4407-4410, Part 1, No. 12B, December 1992.
[10] K. M. Chang, T. H. Yeh, S. W. Wang, and C. H. Li, “Influence of damage and contamination from reactive ion etching on selective tungsten deposition in a low-pressure chemical-vapor-deposition,” J. Appl. Phys., Vol. 80, No. 5, pp.3056-3061,
Era,” IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 2, pp. 267-272, May 1997.
[13] D. Kinkead, M. Joffe, J. Higley, O. Kishkovich, “Forecast of Airborne Molecular Contamination Limits for the 0.25 Micron High Performance Logic Process,”
Technology Transfer # 95052812A-TR SEMATECH, May 31, 1995.
[14] M. Tamaoki, K. Nishiki, A. Shimazaki, Y. Sasaki, S. Yanagi, “The Effect of Airborne Contaminants in the Cleanroom for ULSI Manufacturing Process,” 1995 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, Nov. 13-15, 1995.
[15] J. K. Higley, M. A. Joffe, “Airborne molecular contamination: Cleanroom control strategies,” Solid State Technology, vol. 39, issue 7, pp.211-212, Jul. 1996.
[16] T. Hattori, ‘‘Japanese views on contamination control,’’ Solid State Technology, vol. 37, issue 2, pp.79-80, Feb. 1994.
[17] MA. Rappa, “Future directions in controlling particle contamination in semiconductor integrated circuit manufacturing: an industry survey,” 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, New York, NY, USA, Nov.
14-16, 1994.
[18] R. S. Blewer, “Current and Future Trends in Microcontamination Research,” 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, New York, NY, USA, Nov. 14-16, 1994.
[19] M. Inoue, T. Noda, M. Togawa, H. Inaba, H. Gomi, T. Yoshida, T. Okada, “Study on Boron Contamination in Clean Room,” 12th International Symposium on Contamination Control, Yokohama, Japan, 1994.
[20] T. Jimbo, S. Sakai, K. Katuyama, M. Ito, H. Tomioka, “Thermal desorption behavior of adsorbed materials on wafer surfaces,” 1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, San Fancisco, California, USA, Oct. 6-8, 1997.
[21] D. Kinkead, J. Higley, “Targeting gaseous contaminants in wafer fabs: fugitive amines,”
Microcontamination, vol. 11, no.6, pp.37-40, Jun. 1993.
[22] M. Hashimoto, S. Ichimura, M. Ide, “Testing a chemically reactive filter for the removal of trace hydrogen sulfide gas,” Microcontamination, vol. 12, no. 3, pp.47-53, Mar. 1994.
[23] H. Kitajima, Y. Shiramizu: IEEE Trans. Semiconductor Manufacturing 10 (1997) 267.
[24] D. Kinkead, M. Joffe, J. Higley, O. Kishkovich: Technol. Transfer # 95052812A-TR SEMATECH (1995).
[25] M. Tamaoki, K. Nishiki, A. Shimazaki, Y. Sasaki, S. Yanagi: 1995 IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop, 1995 p.322.
[26] J. K. Higley, M. A. Joffe: Solid State Technol. 39 (1996) 211.
[27] R. S. Blewer: 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop, New York, 1994 p. 83.
[28] M. Inoue, T. Noda, M. Togawa, H. Inaba, H. Gomi, T. Yoshida, T. Okada: 12th International Symposium on Contamination Control, Yokohama, 1994 p. 111.
[29] C. F. Yeh, C. W. Hsiao, S. J. Lin, Z. M. Xie, T. Kusumi, H. Aomi, H. Kaneko, B. T. Da and M. S. Tsai: IEEE-NANO 2002, Proc. 2002 2nd IEEE Conf. Nanotechnology, Washington D.C., 2002 p. 461.
[30] T. Morimoto, T. Ohguro, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, I. Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, and H. Iwai, “Self-Aligned Nickel-Mono-Silicide Technology for High-Speed Deep Submicrometer Logic CMOS ULSI,” IEEE Transactions on electron devices, vol. 42, No. 5, pp.915-922, May 1995.
[31] R. Mukai, S. Ozawa, H. Yagi, “Compatibility of NiSi in the self-aligned silicide process for deep submicrometer devices,” Thin Solid Films, 270, pp.567-572, 1955.
[32] M. C. Poon, F. Deng, M. Chan, W. Y. Chan, S. S. Lau, “Resistivity and thermal stability of nickel mono-silicide,” Applied Surface Science, 157, pp.29-34, 2000.
[33] D. X. Xu, S. R. Das, C. J. Peters, L. E. Erickson, “Materials aspects of nickel Silicide for ULSI applications,” Thin Solid Films, 326, pp.143-150, 1998.
[34] Stephen C. H. Ho, M. C. Poon, Mansum Chan, and H. Wong, “Thermal Stability of Nickel Silicides in Different Silicon Substrates,” IEEE, pp.105-108, Jun. 1998.
[35] B. A. Julies, D. Knoesen, R. Pretorius, and D. Adams, “A study of the NiSi to NiSi2
transition in the Ni-Si binary system,” Thin Solid Films, 347, pp. 201-207, 1999.
[36] L. M. Ephrath, “REACTIVE ION ETCHING FOR VLSI,” IEDM, pp.402- 404, 1980.
[37] K. Tani, T. Yamaji and S. Nishikawa, “Effect of Contact-Hole-Etching Damage on Aluminum Chemical Vapor Deposition,” Jpn. J. Appl. Phys., Vol. 31, pp.4407-4410, Part 1, No. 12B, December 1992.
[38] K. M. Chang, T. H. Yeh, S. W. Wang, and C. H. Li, “Influence of damage and contamination from reactive ion etching on selective tungsten deposition in a low-pressure chemical-vapor-deposition,” J. Appl. Phys., Vol. 80, No. 5, pp.3056-3061, 1 September 1996.
[39] K. Hashimi, D. Matsunaga, M. Kanazawa, M. Tomoyasu, A. Koshiishi and M.
Ogasawara, “Influence of Gas Chemistry and Ion Energy on Contact Resistance,” Jpn. J.
Appl. Phys., Vol. 35, pp. 2494-2500, Part 1, No. 4B, April 1996.
[40] C. F. Yeh and C. L. Chen, “Room-temperature selective growth of dielectric film by liquid-phase deposition,” Semicon. Sci. Technol., vol.9, p.1250, 1994.
[41] C. F. Yeh, Y. C. Lee, and J. L. Su “Selective SiO2-xFx growth with liquid-phase deposition
學 經 歷
姓名：蕭智文
出生年月日：民國 65 年 3 月 20 日
出生地：高雄縣
住址：高雄縣大寮鄉溪寮村 96 號
學歷：國立中興大學 電機工程學系 (83 年 9 月 ~ 87 年 6 月)
國立交通大學 電子研究所 碩士班 (87 年 9 月 ~ 89 年 1 月)
國立交通大學 電子研究所 博士班 (89 年 2 月入學)
論文題目：
微污染與電漿製程對奈米電晶體元件特性影響之研究及其改善方 法之研發
Study on the Effects of Microcontamination and Plasma Process to Nano-Device Characteristics and the Development of Improvement Methods
P
UBLICATIONL
ISTInternational paper:
1. Ching-Fa Yeh, Chih-Wen Hsiao, Wen-Shan Lee, “Novel post CMP cleaning using buffered HF solution and ozone water,” Applied Surface Science, Vol. 216, Issue: 1-4, pp.
46-53, Jun. 2003.
2. Chih-Wen Hsiao, Jen-Chung Lou, Ching-Fa Yeh, Chih-Ming Hsieh, Shiuan-Jeng Lin and Toshio Kusumi, “Impact of Air Filter Material on Metal Oxide Semiconductor (MOS) Device Characteristics in HF Vapor Environment,” Japanese Journal of Applied Physics, Vol. 43, No. 5B, pp. L 659-L 661, 2004.
3. C. F. Yeh, C. W. Hsiao, S. J. Lin, C. M. Hsieh, T. Kusumi, H. Aomi, H. Kaneko, B. T. Da, and M. S. Tsai, “The Removal of Airborne Molecular Contamination in Cleanroom Using PTFE and Chemical Filters,” IEEE Transactions on Semiconductor Manufacturing, Vol.
17, No. 2, pp. 214-220, May 2004.
International conference:
1. C. F. Yeh, C. W. Hsiao, H. C. Lin, L. J. Chen, H. F. Chuang, D. Huang, and C. T. Huang,
“Investigation of Surface Layer on Cobalt Silicide with Different Capping Layer,” 2000 International Electron Devices and Materials Symposia, pp.174-177, Chung-Li, Taiwan, R.O.C., Dec. 20-21, 2000.
2. Ching-Fa Yeh, Chih-Wen Hsiao, Shiuan-Jeng Lin, Zhi-Min Xie, Toshio Kusumi, Hideki Aomi, Hideo Kaneko, Bau-Tong Da and Ming-Shih Tsai, “Impact of Airborne Molecular Contamination to Nano-device Performance,” IEEE-NANO 2002, Proceedings 2002 2nd IEEE Conference on Nanotechnology, pp. 461-464, Washington D.C., USA, Aug. 26-28, 2002.
3. Ching-Fa Yeh, Chih-Wen Hsiao and Wen-Shan Lee, “Novel Post CMP Cleaning Using Buffered HF Solution and Ozone Water,” ISCSI IV, Fourth International Symposium on Control of Semiconductor Interfaces, p. P1-8, Karuizawa, Japan, Oct. 21-25, 2002.
Local Conference:
1. C. F. Yeh, C. C. Hsu, H. M. Shih, and C. W. Hsiao, “Fabrication of Metal-Insulator-Metal(MIM) Diode on the Plastic Substrate with Anodic Ta2O5
Insulator,” 1999 Electronic Devices and Materials Symposium, pp.111-114, Taoyuan, Taiwan, R.O.C., Nov. 25-26, 1999.
2. C. F. Yeh, C. W. Hsiao, C. C. Chen, and C. C. Hsu,
“Metal-Induced-Lateral-Crystallization (MILC) crystallization rate investigation for different α–Si films,” 1999 Electronic Devices and Materials Symposium, pp.401-404, Taoyuan, Taiwan, R.O.C., Nov. 25-26, 1999.
3. Ching-Fa Yeh, Wen-Hsin Chan, and Chih-Wen Hsiao, “Thermal stability of nickel monosilicide on different silicon films,” Electronics Devices and Materials Symposia Taiwan’01 Proceeding, pp. 95-98, Kaohsiung, Taiwan, R.O.C., Dec. 12-13, 2001.
4. Ching-Fa Yeh, Chih-Wen Hsiao, and Wen-Hsin Chan, “Implementation of nanometer gate using selective liquid phase deposition technology,” Electronics Devices and Materials Symposia Taiwan’01 Proceeding, pp. 423-425, Kaohsiung, Taiwan, R.O.C., Dec. 12-13, 2001.
Patent:
1. 蕭智文，羅正忠，陳昶維，“利用液相沉積法成長高介電常數材料＂，中華民國專利 申請中。