4.1 I NTRODUCTION
4.3.4 Thermal Stability of NiSi
In the MOSFET fabrication, some thermal processes were used after the silicidation process. Such as the PE-TEOS deposition, low K dielectric curing and aluminum sintering, etc. These process temperatures are usually below 800℃ to prevent the dopant redistribution.
In this section, the thermal stability of NiSi was tested by the 2nd RTA at the temperatures ranging from 500℃ to 800℃ for 30s.
Figure 4-14 shows the sheet resistance of NiSi formed with 200Å thick Ni at different RTA-1 temperature. The samples with the RTA-1 temperature ranging from 400℃ to 600℃
were used to do the thermal stability tests.
For NiSi on c-Si, as shown in Fig. 4-15, the sheet resistances of NiSi formed at different RTA-1 temperature are stable after below 700℃ RTA-2 for 30s. The high temperature of 800℃ results in the relatively high sheet resistance with the transition of lower resistivity NiSi phase to higher NiSi2 phase. Figure 4-16 shows the sheet resistance of NiSi on poly-Si at different RTA-2 temperature for 30s. We found the sheet resistances of NiSi formed at different RTA-1 temperature are still low after below 600℃ RTA-2, but become very high after above 700℃ RTA-2. Figure 4-17 shows the sheet resistance of NiSi on a-Si at different RTA-2 temperature for 30s. They are stable even after 800℃ RTA-2. Figure 4-18 shows the sheet resistance of NiSi on apoly-Si at different RTA-2 temperature for 30s. We could see the sheet resistances increase at 700℃ RTA-2 and become high at 800℃ RTA-2. After the thermal stability testing, Ni silicide on a-Si owns the best stability. But for NiSi on c-Si, Ni will continuous diffuse and increase the sheer resistance. Compared to the columnar poly silicon, the non-columnar poly silicon is more stable in the same thermal treatment.
4.4SUMMARY
In this chapter, we investigated the sheet resistance behavior of Ni silicide on different substrates. We found the planer NiSi formed with 200Å thick Ni is stable and shows low sheet resistance between 400℃ and 650℃ RTA-1, and still stable after 700℃ RTA-2 for 30s on c-Si and apoly-Si. In the same experiment, the planer NiSi on poly-Si shows low sheet resistance below 600℃ RTA.
After the SEM micrographs observation, we found the different surface morphology of Ni silicide on poly-Si, a-Si, and apoly-Si. At the lower RTA temperature, the surface is more uniform. As the dark spots or agglomeration appear, the sheet resistance begins to increase. At the higher RTA temperature, the surface of Ni silicide on poly-Si and apoly-Si seem micro-crack or agglomeration which results in the higher sheet resistance.
As the research of the linewidth effects of NiSi sheet resistance on poly-Si, a-Si, and apoly-Si, we found the appearance of dark spots or agglomeration would affect the sheet resistance of Ni silicide seriously. For 600℃ RTA on poly-Si and apoly-Si, the sheet resistances of Ni silicide increase. Even so, it is more obvious with the narrower linewidth.
We notice that behavior of NiSi sheet resistance at 600℃ RTA on a-Si is similar to that on apoly-Si. This is due to the effect of dopant activation at 1000℃ for 30s RTA. Due to the linewidth effects, the process window of NiSi RTA temperature is ranging from 400℃ to 550℃.
In the last section of this chapter, we tested thermal stability of Ni silicide by the 2nd RTA at the temperatures ranging from 500℃ to 800℃ for 30s. Ni silicide on a-Si owns the
TABLE 4-1
Silicon Consumption and Film Stress for Various Silicides
Silicide Silicon Consumption
Silicidation Temperature(oC)
Film Stress (dyn/cm2) NiSi 0.82 × TNiSi 350 ~ 750 6 × 109
NiSi2 1.02 × TNiSi2 750 ~ 850 -
TiSi2 0.90 × TTiSi2 800 ~ 950 1.5 × 1010
CoSi 0.91 × TCoSi 375 ~ 500 -
CoSi2 1.04 × TCoSi2 550 ~ 900 1.2 × 1010
TABLE 4-2
Sheet Resistance of As-deposited Nickel on Different Substrates
As-deposited nickel thickness Substrate
100Å 150Å 200Å 200Å/Ti cap100Å
c-Si 25.9 13.8 8.9 8.2
poly-Si 36.2 16.5 11.8 10.3
a-Si 30.4 14.3 10.3 9.3
apoly-Si 33.4 15.8 9.8 7.3
unit: Ω/□
Å
3. Å
Å Å
Å
Å Å 18.
Fig. 4-2. Fabrication process flow of poly-line with nickel silicide.
350 400 450 500 550 600 650 700 750 800
RTA-1 Temperature (oC)
Fig. 4-3. Sheet resistance of NiSi formed on c-Si.
10
350 400 450 500 550 600 650 700 750 800
RTA-1 Temperature (oC)
Fig. 4-5. Sheet resistance of NiSi formed on a-Si.
350 400 450 500 550 600 650 700 750 800
0
RTA-1 Temperature (oC)
Fig. 4-6. Sheet resistance of NiSi formed on apoly-Si.
(a) 500℃ (b) 550℃
(c) 600℃ (d) 650℃
(e) 700℃ (f) 750℃
Fig. 4-7. Top view SEM micrographs of Ni-silicide on poly-Si at different RTA
(a) 500℃ (b) 550℃
(c) 600℃ (d) 650℃
(e) 700℃ (f) 750℃
Fig. 4-8. Top view SEM micrographs of Ni-silicide on a-Si at different RTA temperature.
(a) 500℃ (b) 550℃
(c) 600℃ (d) 650℃
(e) 700℃ (f) 750℃
Fig. 4-9. Top view SEM micrographs of Ni-silicide on a-poly Si at different RTA
Fig. 4-10. Bridge resistor structure.
0.5 0.6 0.7 0.8 0.9 1.0 0
10 20 30 40
400oC 500oC 550oC 600oC
Sheet Resistance, Rs (Ω/sq.)
Linewidth (µm)
Linelength = 500µm
Fig. 4-11. Sheet resistance of different linewidth NiSi formed on poly-Si.
50 100 150 200
400oC 500oC 550oC 600oC
Sheet Resistance, Rs (Ω/sq.)
Linelength = 500µm
0.5 0.6 0.7 0.8 0.9 1.0
Fig. 4-13. Sheet resistance of different linewidth NiSi formed on apoly-Si.
350 400 450 500 550 600 650 700 750 800
0
RTA-1 Temperature (oC)
Fig. 4-14. Sheet resistance of NiSi formed with 200Å thick Ni.
0 500 600 700 800 900 0
5 10 15 20
RTA-1 Temperature 400oC
450oC 500oC 550oC 600oC
Sheet Resistance, Rs (Ω/sq.)
RTA-2 Temperature (oC)
Fig. 4-15. Sheet resistance of NiSi on C-Si for RTA-2 annealing.
10 20 30 40 50
RTA-1 Temperature 400oC
450oC 500oC 550oC 600oC
Sheet Resistance, Rs (Ω/sq.)
0 500 600 700 800 900
RTA-2 Temperature (oC)
Fig. 4-17. Sheet resistance of NiSi on a-Si for RTA-2 annealing.
0 500 600 700 800 900
RTA-2 Temperature (oC)
Fig. 4-18. Sheet resistance of NiSi on apoly-Si for RTA-2 annealing.
C
HAPTER5
Investigation of Plasma Damage-Free Selective Liquid-Phase Deposition to Contact-Hole Formation
5.1INTRODUCTION
When device continuously scales down, the source/drain engineering becomes important and complex. With the MOSFET gate length scaling down to sub-100nm, the source/drain process almost reaches the limit. Many new technologies and materials have adopted to overcome these difficulties. Silicide is one key technology for solving these problems. As the gate length scales, the source/drain junction depth must shrink at the same time to decrease the short channel effects. Owing to the shallower junction depths than before, the resistance of junction becomes high. Silicide provides a new choice to lower the junction parasitic resistance. Titanium, cobalt and nickel are the popular materials to form silicide. Due to the line-width effect and thermal stability problems, titanium silicide is not suitable for future device manufacturing. Cobalt silicide is the most used material for sub-0.18µm technology. To reach the ultra-shallow junction, the high consumption of silicon to form cobalt silicide may be the weakness for further shrink device geometry. Nickel silicide is the promising material for future advanced device manufacturing because of its low silicon consumption, low resistivity and lack of line-width effect.
Reactive ion etching (RIE) is the most frequently used technology for contact-hole
layer [37]-[39]. The radiation damage results from the energetic ions accelerated by DC bias.
The surface amorphized layer comes from the ion bombardment damage to junction surface.
And the contaminated layer is due to the fluorocarbon-containing based etching chemistries.
This damage layer is around hundred of angstroms deep from the surface. Some technologies [37], [38] are used to eliminate this surface damage layer including high temperature annealing, surface etching, etc. But these methods may not suitable for silicide process and ultra-shallow junction when manufacturing ULSI.
In our study, we proposed a novel selective liquid-phase deposition (S_LPD) process to overcome these problems. S_LPD process is the selective deposition technology which deposits oxide on silicide surface against contact-hole defined photoresist. This technology is conduct under non-plasma environment and hence it will not induce the surface damaged and contaminated layer. The experimental results indicate that the novel S_LPD process indeed has the superior of suppressing plasma damage on ultra-shallow junction. Therefore, the novel S_LPD process will become the candidate of non-plasma process for future advanced device manufacturing.