Silicon Interface
2.2 Experimental Details
All the samples used in this experiment were prepared by low pressure chemical-vapor deposition process and the deposition process was carried out in an induction-heated hot-wall horizontal reactor using mono-silane (SiH4) gas as a silicon source. P-type (100)-oriented silicon wafers with a resistivity of 8~12 ohm-cm were used as substrates. The conventional poly-Si films were deposited at a fixed temperature (630 °C) while a-Si films were deposited at two different temperatures:
540 °C and 560 °C and all the deposition pressure was 0.11 torr. The thickness of the poly-Si and a-Si films were about 4000 Å and 3000 Å, respectively, irrespective of the deposition temperature. According to the results on the phase dependence of deposition condition [15,17], we have chosen the deposition temperature of 560 °C and an even lower temperature of 540 °C to ensure that the as-deposited phase is a-Si.
The stacked poly-Si films were deposited at 630 °C for 30 min., before decreasing the temperature down to 560 °C with a rate of 3 °C / min. The temperature was then held at 560 °C for 60 min without interrupting the deposition process, the total thickness
was about 4000 Å. The as-deposited film was then doped with n-type phosphorus using POCl3 gas at 950 °C and atmospheric pressure in an induction-heated hot-wall horizontal reactor. After a 5 % HF solution deglazing for 3 min and RCA SC-1/SC-2 cleaning [21], atomic force microscope (Topometrix Explorer) with a resolution of 300 x 300 pixels was employed in contact mode to analyze the surface roughness.
TEM (Phillips Tecnai 20 with field emission gun) interface analysis was made after oxidizing the doped poly-Si films at 950 °C and atmospheric pressure by dry oxidation, leading to a polyoxide thickness about 250 Å. The cross-sectional thin foils were prepared by mechanical thinning to 30 µm in thickness, followed by Ar+ ion thinning (5 KeV, 8° for 20 min) until perforation. TEM was operated at 200 KeV and images were acquired with a Gatan CCD camera. Electrical characteristics of MOS dielectric films were measured by a HP4145B semiconductor parameter analyzer. The breakdown voltage was determined by ramp-voltage breakdown test with a ramp rate of 0.1 V/sec on a area of 70 x 70 µm2 and the breakdown criteria was 1 µA. A X-ray diffractometer (Diano 700) with Cu Kα radiation was employed to determine the texture microstructures of thin-films.
2.3 Results
Figs. 2-1(a), 2-1(b), 2-1(c) and 2-1(d) are the AFM images of doped a-Si (540
°C and 560 °C), doped poly-Si (630 °C), and doped stacked poly-Si films, respectively. From these images, it is clear that the doped a-Si films have apparent protrusions on the surface, (Figs. 2-1(a) and 2-1(b)), although most part of the surface area is smoother than that of conventional doped poly-Si and stacked poly-Si films.
Their corresponding line scans are also shown in Fig. 2-1 to demonstrate the variation of the surface roughness. Previous studies [15-18] attributed these protrusions to the appearance of a (311) texture after annealing of doped a-Si film. X-ray analysis result (Fig 2-1(e)) can clearly see doped a-Si has highest (311) texture ratio, consistent with the previous studies [15-18]. Also we can see the stacked poly-si has least (311) texture ratio, even less than poly-Si. This protrusion will induce local electric field enhancement after oxidation. Because of the protrusion, doped a-Si films have high surface roughness counts with root-mean square surface roughness (Rrms) of 192 Å (540 °C) and 123 Å (560 °C), respectively. On the other hand, doped conventional (630 °C) poly-Si films (Rrms = 97 Å) and doped stacked poly-Si films (Rrms = 78 Å) have much smaller roughness than the a-Si /poly-Si. From the AFM images, it is also observed that doped stacked poly-Si films have narrow grain size distribution, compared with conventional doped poly-Si. The morphology of conventional doped poly-Si was sharper than stacked doped poly-Si films.
Figs. 2-2(a) and 2-2(b) are the TEM images of oxide/poly-Si interface for
conventional doped poly-Si and doped stacked poly-Si, respectively. From Fig 2-2(a), the doped conventional poly-Si films have (110) columnar grain structure, resulting in straight grain boundaries from polyoxide to the substrate and high angle grain boundaries in the oxide/poly-Si interface. These high angle grain boundaries were induced by the (110) texture columnar structure of doped poly-Si [15-18]. They will induce electric field enhancement, leading to a high leakage current in this area.
Because of the recrystallization of a-Si on poly-Si, the doped stacked poly-Si layers do not exhibit (110) texture structure.
Fig. 2-3 shows the Weibull plots of electrical characteristics of doped stacked poly-Si versus conventional poly-Si films. For MOS capacitor applications, high charge to breakdown and high breakdown field are critical requirements to device performance. From the plot, clearly, higher breakdown voltage was observed for the dielectric film grown on stacked poly-Si. Enhanced electric field of MOS capacitor can be achieved in this case. It can be seen that the conventional poly-Si shows a much wider distribution of breakdown voltages than the stacked poly-Si. That is, the surface roughness of poly-Si film interface is higher than that of stacked poly-Si film.
2.4 Discussion
According to the above results, one can see that doped a-Si films have a higher
surface roughness than poly-Si. Poly-Si contains less (311) phase, but, instead, its (110) phase results in columnar grain structure, which induces high angle grain boundaries after oxidation and degradation in its breakdown strength. Fig. 2-2(c) is a magnified image of Fig. 2-2(a) around the grain boundary region. It is shown more clearly that, due to the high angle grain boundary, oxide forms an inverted triangle shape with sharp tip at a region adjoining two neighboring grains, causing a groove on surface. The thickness of the inverted triangle oxide is about 125 Å, half of the normal oxide thickness 250 Å. This structure seriously increases the roughness of oxide/poly-Si interface and easily results in local electric field enhancement at this region, which further induces higher leakage current and lower dielectric breakdown field. Fig. 2-2(d) is a schematic representation of the oxide/poly-Si interface in detail.
From Fig. 2-2(d), we can see that because the poly-Si is the periodic (110) columnar structure, it means that the inverted triangle oxide with surface groove also assume the periodic pattern. Therefore, the dielectric breakdown strength of poly-Si is limited by this structure. On the other hand, from Fig. 2-2(b), the doped stacked poly-Si films with random grain structure do not have apparent periodic high angle grain boundaries, and thus prevent this issue. Apparently, both the doped a-Si and poly-Si suffered from the texture-induced surface roughening effect, and how to control the texture becomes a very important issue to device reliability.
The stacked poly-Si films contain a top a-Si layer and a bottom poly-Si layer.
The top a-Si layer will recrystallize after impurity doping. Wang et al. [20] found that the recrystallization of a-Si film (deposited below 600 °C) results in poor crystallinity and low-angle grain boundaries, which give rise to smoother surface. As a consequence, the stacked poly-Si films should have a smoother surface than conventional poly-Si films. From the AFM image (Fig 2-1(d)), one can also see that the recrystallization of the top layer of doped stacked poly-Si contains no distinct textures on the surface just as the doped a-Si did. Because of this recrystallization behavior, the upper layer of stacked poly-Si contains randomly oriented grain boundaries, it also contains no (110) columnar grain structure on the surface. This suggests that the doped stacked poly-Si can improve both the adverse texture effects of doped a-Si and doped poly-Si. This explains why the doped stacked poly-Si structure has a smoother surface and better electrical performance than the other two.
2.5 Conclusions
In this study, doped stacked poly-Si films with lower surface roughness and smoother poly-Si/polyoxide interface than doped a-Si and conventional poly-Si films are developed. This new stacked poly-Si film has the poor recrystallization- induced crystallinity as in a-Si but no protrusion on surface and no apparent high angle grain
boundaries. Results of electrical breakdown voltage measurements also show that the doped poly-Si film stack has a better performance than the doped conventional poly-Si film.