Gate delay is the time between gate input transition and gate output transition, when they reach 50% VDD. Nominal gate delay (d) is the gate delay without PSN, which is
obtained from the standard delay format (.sdf) file. Δd is the PSN-induced extra gate delay. We need to estimate Δd for every switching gate so that we can calculate the gate
delay (d*) under PSN effect.
d* d d (3.4)
Figure 3.4 shows an inverter with rising output. We use gate 1 and gate 2 to represent a driver gate and a receiver gate, respectively. In this thesis, we use this figure as an illustration example to estimate gate delay. vI1 and vI2 are input voltage of gate 1 and gate 2, respectively. vO1 and vO2 are output voltage of gate 1 and gate 2, respectively.
They are functions of time, so they are denoted in small letters.
C
Figure 3.4 Example of rising gate delay estimation of gate 2
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To estimate ΔdR2, which is the rising extra gate delay of gate 2, we use
* estimated rising gate delay of inverter 2 with PSN. In this thesis, the hat symbol means the value is estimated and the asterisk symbol means the value is PSN-aware.
Figure 3.4(b) shows how to estimate R2. Equation (3.6) is used in the estimation.
( )2
D 2 GS TH
i v V
(3.6) , where iD is the drain current through MOS, β is the transconductance coefficient of MOS, vGS is the voltage between transistor gate and source and VTH is the threshold voltage of MOS. Although we use level-1 quadratic model in this derivation, the conclusion of our work can be applied to other more accurate models. We will show that the conclusion is insensitive to the model in the Discussion Chapter. β and VTH can be accessed in the
MOS model, not in gate-level simulation. Therefore, two approximations are used to obtain ΔdR2, which will be detailed below.
iD represents the current flowing out of P. One part of iD is the short circuit current, which flows into G. The other part of iD is switching current, which flows into the capacitor. The former is about a hundred times smaller than the latter. Therefore, we assume that switching current is equal to iD.
In Figure 3.4, since vGS changes during input transition, R2 estimation is divided into
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two parts. One is the delay before vI2 reaches its GND; the other is the delay after vI2
reaches GND. The former is equal to half of input transition time of gate 2, which is equal to half of output transition time of gate 1. τF1 is the falling output transition time of gate 1. The latter is defined as δR2. the delay after vI2 reaches GND, as shown in equation (3.13), by substituting equation
(3.10) into equation (3.12). δR2 is measured as the delay from vO2=VR2 to vO2=0.5VDD.
25 input slope of gate 2 with PSN effect.
* 2 2 1
ΔτF1 is the PSN-induced extra falling output transition time of gate 1. The estimation of ΔτF1 will be detailed below.
In Figure 3.5, the waveform shows the output transition considering PSN. VH0 and VL0 are the power voltage of gate 0 and ground voltage of gate 0. VH1 and VL1 are the power voltage of gate 1 and ground voltage of gate 1. VH2 and VL2 are the power voltage of gate 2 and ground voltage of gate 2.
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Figure 3.5 Example of I/O waveform considering PSN
To obtain the values of power voltage and ground voltage for every gate, we solve
G V + C V = I matrix to calculate average PSN and average ground bounce. The I
vector is obtained from TABLE 3.1. Silicon data have been shown that average PSN correlates well with extra gate delay [Saint-Laurent 2004][Ogasahara 2007][Hashimoto 2008]. Values of VH0, VH1 and VH2 can be substituted by VDD minus average PSN of
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Output transition time is the time between GND and VDD of gate output transition.
Nominal output transition time (τ) is the output transition time without PSN, which can be obtained from the .lib file. Δτ is the PSN-induced extra output transition time, which is needed for estimating output transition time (τ*) under PSN effect.
We use a model to calculate output transition time, which is proposed in [Maurine 2001]. In equation (3.20), τ F1 and τ * F1 are the estimated falling output transition time of
inverter 1 without PSN and with PSN, respectively.
* we use peak current to replace the current in these equations, like equations (3.21) and (3.22).
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To calculate the value of peak current, we use the equalization of charge to explain the derivation. Equation (3.23) shows the integral of iD and we assume dR2≫0.5τF1. One part of iD is the short circuit current. Since the duration of dR2 only include half of input transition time, the charge is equal to 0.5×QIN. The other part of iD flows through the capacitor for charging. Since the range of vO2 variation during dR2 is 0.5×VDD, the charge is equal to 0.5×QSW. Therefore, QD is equal to 0.5×(QIN+QSW). I̅PR2 is I̅PR of
We substitute equation (3.23) into equation (3.24) and obtain
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Therefore, ĨPR2 in equation (3.21) is obtained.
2 2
Figure 3.6 Current waveform transformation
Similarly, Ĩ * PR2, ĨGF1 and Ĩ * GF1 in equations (3.21) and (3.22) are calculated by:
We substitute equations (3.37) to (3.39) into equations (3.21) and (3.22) and obtain equations (3.30) and (3.31).
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In these two equations, we model extra gate delay and extra output transition time as function of charges, but not current model. Therefore, the impact of applying
different drain current model is small.
We use similar way to estimate ΔdF2 and ΔτR1, as shown in equations (3.32) and and with PSN, respectively.
2 1
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