We model extra gate delay and extra output transition time as function of charges, but not current model. Therefore, the impact of applying different drain current model is small.
Since we use level-1 current model in extra gate delay estimation, we analyze the impact of more accurate model in this section. We apply another current model on extra gate delay estimation to analyze the impact.
We use equation (5.14) as an example of another drain current model and use Figure 5.5 as an illustration example of rising gate delay estimation. Since the following estimation is similar to the estimation in Section 3.3, we only show the difference caused by the new current model.
31
D 2 GS TH
i v V (5.14)
53
Figure 5.5 Rising gate delay estimation for an inverter
Since vGS changes during input transition, R2 estimation is divided into two parts.
2 1 2
1
R 2 F R
d (5.15)
One is the delay before vI2 reaches its GND; the other is the delay after vI2 reaches GND.
The former is equal to half of input transition time of gate 2, which is not influenced by current model. The latter is defined as δR2, as shown in equation (5.16).
The derivation of VR2, which is the output voltage when vI2 reaches GND, is shown in equations (5.17) to (5.19).
54 current in equation (5.22).
2
55
We substitute equation (5.24) into equation (5.25) and obtain
2Therefore, ĨPR2 can be calculated by
2 2 1 influenced by different current model as long as the assumption of dR2≫0.5τF1 is valid.
56
Second, we deal with 4SI2 and 4S* I2, which are in the denominator of equation (5.23).
Since SI2 and S* I2 are very large, we can make this approximation:
2 1 2 1
* *
2 2 2 2
3 3 4 4 0
H L H L
I I I I
V V V V
VDD VDD
S S S S
(5.29)
Therefore, the impact of different drain current model on extra gate delay estimation is very small.
57
6
Chapter 6 Conclusion and Future Work
This thesis proposes an efficient and accurate PSN-aware dynamic timing analyzer, IDEA, which considers both IR-drop and Ldi/dt. IDEA uses window partition to calculate average PSN in a window so that we can find good balance between accuracy and runtime. IDEA is very scalable because the gate delay is modeled as a function of charges. Therefore, IDEA estimates gate delay accurately without SPICE simulation for each logic gate. The experimental results show, for small circuits, the average error of total path delay is less than 1% compared with HSPICE. For large circuits, we achieved eight times speed up compared with NANOSIM.
After performing IDEA on a 1M gate benchmark circuit, experimental results show that 369 timing-violation test patterns (out of 31K test patterns) are identified. A test pattern modification is needed by these test patterns to prevent timing failure and avoid yield loss. Previous research papers about test pattern modification do not handle timing-violation well since they do not have good techniques to translate PSN to extra gate delay. Existing techniques modify test patterns to minimize power for critical paths [Wen 2007][Enokimoto 2009][Miyase 2011]. X-filling is used to reduce switching activity at neighboring logic gates near critical paths [Wen 2007][Miyase 2011]. Clock-gating and FF-silencing are applied on flip-flops, which are in the fan-in cone of neighboring logic gates near critical paths [Enokimoto 2009]. However, there are two
58
problems in these previous research papers: (1) how to determine the range of neighboring logic gates and (2) how to guarantee timing-safety after test pattern modification. We use Figure 6.1 to illustrate the first problem. Logic gates in critical area (radius R) are neighboring logic gates. The value of R is hard to determine since it is unwarrantable that the impact of logic gates outside the critical area can be ignored. For the second problem, these techniques only reduce power consumption without considering timing.
Therefore, the test patterns are power-safety after test pattern modification, but not always timing-safety.
Figure 6.1 Neighboring logic gates near critical path [Enokimoto 2009]
Nowadays, by means of IDEA, we can obtain PSN-induced extra gate delay accurately and efficiently. Once we develop a novel tool, which modifies timing-violation test patterns without test length inflation and fault coverage loss, we can obtain a timing-safety test set even for large circuits with lots of test patterns.
59
7
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