Eye Diagram

A transmitter delivers signals based on a kind of selected interface specification. When long stream bits of data are conveyed, it is inefficient and non-smart to check the bits one by one. Therefore, an eye diagram is made to understand the characteristics of transmitted bits conveniently.

An eye diagram of a signal overlays the signal’s waveform over many cycles. Each cycle’s waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. The vertical thickness of the line bunches in an eye diagram indicates the

magnitude of AC voltage noise; whereas the horizontal thickness of the line bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen. The size of the eye opening in the center of an eye diagram indicates the amount of voltage and timing margin available to sample this signal. Thus, for a particular electrical interface, a fixed reticule or window could be placed over the eye diagram showing how the actual signal compares to minimum criteria window, know as the eye mask. If a margin rectangle with width equal to the required timing margin and height equal to the required voltage margin fits into the opening, then the signal has adequate margins.

Chapter 3

Phase-Locked Loop

3.1 Introduction

Phase-locked loops (PLL) are analog building blocks used extensively in many analog, digital and communication systems. Their use has become attractive for many applications such as clock recovery, frequency synthesizers, FM demodulators and others. These are only few applicable areas, but PLL has undoubtedly become an important building block in many electronic systems. Recently, as the needs for high speed data transmissions rise, the PLL technique plays a key role to implement the demand. In this chapter we first explore the architecture of the PLL, and then explain the circuit implementations for the PLL to achieve the clock rate at 1GHz. In this transmitter, we need a pair of complementary clock signals with 1GHz frequency to trigger the output driver. The detailed discussion of the transmitter operation will be shown in next chapter. The linear model, the noise and the stability are all taken into consideration in 3.4 and 3.5, followed by a section discussing the flow of design and the way to make proper decision on loop parameters of the PLL. The simulation results are presented in the final section of this chapter.

3.2 Architecture of PLL

Fig. 3-1 shows a block diagram of the basic PLL system. The system consists of a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider. The VCO is simply an oscillator whose frequency is proportional to an externally applied voltage. Before inputting the clock at reference frequency (Ref_CLK), the VCO oscillates at its free-running frequency. When the Ref_CLK signal is input, the phase/frequency detector detects both the Ref_CLK and the feedback signal (Fb_CLK). Afterward the detector and the charge pump produce a dc or low frequency signal proportional to the phase difference between Ref_CLK and Fb_CLK. The loop filter acts as a low pass filter and is used to extract the average value from the output of the charge pump. This signal is then amplified and used to drive the VCO. The VCO’s oscillation frequency will be changed by the control voltage (Vctrl) according to the reference frequency. A frequency divider being used in the diagram, the output clock’s frequency of the VCO will be N times of the Ref_CLK signal. When the loop is locked, the negative feedback of the loop results in the output of the VCO being synchronized with the input signal. Moreover, the input signal (Fref) and the feedback signal (Fb) are phase-aligned. The PLL turns out to be able to lock to the input signal successfully.

Fig. 3-1 Functional block diagram of charge pump PLL

3.3 Circuit Implementation

3.3.1 Phase/Frequency Detector

The phase/frequency detector (PFD) is a digital sequential circuit built based on a tri-state operation. It is used to detect the phase difference between the reference (Ref_CLK) and the feedback (Fb_CLK) signals. Fig. 3-2 shows the implementation of PFD [7][8]. The PFD is composed of two high speed TSPC (True-Single-Phase-Clocking [9]) D-flip flops, a NOR gate, inverters and a buffer in the reset path.

Fig. 3-2 Phase/Frequency detector with TSPC D-flip flops

The PFD is triggered by the positive edges of the Ref_CLK and the Fb_CLK. It detects the phase difference between them and outputs two signals, UP and DOWN, to represent the phase relationship of them as shown in Fig.3-3. If the Ref_CLK and the Fb_CLK are in

phase, the output waveforms of UP and DOWN will be the same. The controlled voltage and the oscillation frequency of the VCO remain invariable.

Fig. 3-3 Operation of PFD

When the Fb_CLK lags the Ref_CLK, the UP signal will be switched from low to high first. This will in turn increase the frequency of the VCO and the Fb_CLK signal. Then the positive edge of the Fb_CLK arrives and the DOWN signal will be switched from low to high, too. When both UP and DOWN signals are set at high, the reset signal will thus be turned to high in order to reset them to low. The comparison between Ref_CLK and Fb_CLK in this cycle is finished. In contrast, if the Fb_CLK leads the Ref_CLK, the output signals, UP and DOWN, of PFD will be used to decrease the frequency of the VCO and the Fb_CLK signal. This type of operation has a linear range of ±２ and can act as both a π phase detector and a frequency detector. This property will greatly enhance the locking range.

A low precision PFD has a wide dead zone as shown in Fig. 3-4, which results in increased jitter. Ideally, the PFD should have the ability to distinguish any phase error between Ref_CLK and Fb_CLK. The dead zone will occur in practical exercises when the loop is in a lock mode and the PFD cannot detect the small phase difference of Ref_CLK and Fb_CLK. The detected phase error will thus remain zero and this will result in an increase of unavoidable jitter of the PLL.

Fig. 3-4 The PFD dead zone

The delay buffer in the reset path is used to avoid the occurrence of dead zone. For in-phase inputs of Ref_CLK and Fb_CLK, the charge pump will see both UP and DOWN pulses for the same short period of time. If there is a phase difference between Ref_CLK and Fb_CLK, the width of UP and DOWN pulses will be proportional to the phase difference of the inputs. Fig.3-5 shows the SPICE simulation result of the proposed PFD circuit.

Phase Difference between Ref_CLK and Fb_CLK (ps)

UP pulse width - DOWNB pulse width (ps)

Fig. 3-5 simulation result of PFD without dead zone

3.3.2 Charge Pump

The charge pump (CP) cooperates with the PFD to change the control voltage of the VCO. The circuit implementation of the charge pump is shown in Fig. 3-6 [10]. It can charge and discharge the capacitance of the loop filter to vary the Vctrl according to UP and DOWNB signals from the PFD. There are some problems in conventional charge pump circuits such as charge injection and clock feed through. These problems will result in a phase offset at the input of the PFD when the PLL is locked. In order to overcome these problems, the two switch devices are separated from the output voltage. Therefore, the output voltage is now isolated from the switching noise resulting from the overlap capacitance of the two switch devices. In addition, the intermediate node between the current source and switch devices will charge to the output voltage only by the gate overdrive of the current source devices, Vgs –Vt, an amount independent of the output voltage. The charge pump circuit can therefore control Vctrl and successfully reduce the static phase offset.

Fig. 3-6 Schematic of the charge pump

3.3.3 Loop Filter

The loop filter (LF) is a low pass filter used to extract the average value from the charge pump output. The schematic of the loop filter is shown in Fig. 3-7. It is usually composed of a resistor R1 in series with capacitor C1 and a capacitor C2 in parallel.

Fig. 3-7 Schematic of the loop filter

The loop filter provides a pole in the origin to provide an infinite DC gain so as to minimize the static phase error. The resistor R1 and capacitance C1 provide a zero in the open loop response in order to improve the phase margin to ensure overall stability of the loop. Finally, the use of the capacitance C2 is to reduce the ripple noise on Vctrl to mitigate the frequency jump. The transfer function of the loop filter can be expressed as

( )

The use of the capacitance C2 will make the overall PLL system third-order and affect the stability of the loop. In general, when the capacitance C2 is much smaller than C1, the third-order loop can be approximated to a second-order one.

3.3.4 Voltage Controlled Oscillator

The building blocks of the VCO include a replica-feedback current source bias circuit, a two-stage ring oscillator, differential-to-single-ended converter circuits and duty-cycle corrector circuits as shown below.

Fig. 3-8 Architecture of the VCO

The VCO is eventually designed to produce four full swing clock signals, F0~F3, at 1GHz frequency. In order to achieve low jitter operation, the circuit should have low power and substrate noise sensitivity. The VCO design is based upon the differential buffer delay cells with symmetric loads and replica-feedback biasing.

The replica-feedback current source bias circuit, shown in Fig. 3-9 [11], produces the bias voltages Vbp and Vbn from Vctrl. It is used to continuously adjust the buffer bias current to provide the correct lower swing limit of Vctrl for the buffer delay cells. If the supply voltage changes, the differential amplifier will adjust to keep the swing and thus the bias current constant. In so doing, it establishes a current that is held constant and independent of supply voltage. Besides, the bias generator also provides a buffered version of Vctrl at the Vbp output using an additional Vctrl buffer. The buffer can isolate the control voltage Vctrl

from the capacitive coupling of the VCO delay cells.

Fig. 3-9 the replica-feedback current source bias circuit

In order to achieve the goal of high speed and low power consumption, the two-stage ring oscillator architecture is chosen [12][13]. However, a conventional differential delay cell fails to satisfy the oscillation conditions. If the conventional delay cell is used in a two-stage ring oscillator, the system will not oscillate because the gain is under 0dB at the frequency in which the absolute phase changes 90°(180°/N), causing the insufficient gain problem. Therefore, the circuit implementations of the proposed delay cells are shown in Fig. 3-10. The designed characteristics are obtained by means of the positive partial feedback.

Fig. 3-11 Half-circuit and small signal model of a delay cell

As shown in Fig. 3-11, the transfer function of the proposed delay cell can be written as below

where gm and gma are respectively the transconductances of M1-M2 and M1a-M2a, Cgd is the gate-drain capacitance of M1-M2, CL is the capacitance associated with one of the output nodes and R is the resistance of the symmetric load.

The symmetric load consists of a diode-connected PMOS device and an equally sized PMOS device as shown in Fig. 3-12. The effective resistance of it is directly proportional to the small signal resistance at the ends of the swing range which is just one over the transconductance for one of the two equally sized devices. The symmetric load can also cancel the first order of the common mode voltage noise. Therefore, it is used to have high dynamic supply noise immunity and provide high small-signal resistance.

Fig. 3-12 Typical symmetric load and I-V characteristic

Substituting s=jω in the phase of equation (3-3) and making it equal to 90°, the oscillation frequency of the VCO is given by

z p

ω = ω ω ×

(3-5) The current source Ivco, shown in Fig. 3-10, enables the establishment of a minimum current in the delay cells. The oscillation frequency does not disappear even when the control voltage does not fall in its nominal range. On the other hand, the VCO oscillates at an essential frequency. This can reduce the amount of the KVCO to decrease the negative effect caused by the noise for the PLL.

The output clock signals from the delay cells swing in a small range and additional circuits are required to become full swing. In Fig. 3-13, the schematic of differential-to-single-ended converter is presented to amplify the input signals. According to Vbn, the circuit corrects the input common-mode voltage level and provides signal amplification.

Fig. 3-13 Schematic of differential-to-single-ended converter

Maintaining a 50% duty-cycle ratio for clock signals is extremely important. The feedback clock signal to the PFD also needs a 50 % duty-cycle single-ended signal. The duty-cycle corrector [14], as shown in Fig. 3-14, utilizes multiphase signals generated from the two-stage differential VCO. The signals, Vo+ and Vo-, are used to charge and discharge the output node alternately. Since this duty-cycle corrector consists of only two transmission gates and two inverters, the silicon area is minimal and the power consumption is negligible.

Fig. 3-14 Feed forward-type duty-cycle corrector schematic

The PLL used in this thesis has to output four clock signals at 1GHz frequency. The oscillation frequency range of the VCO needs to fit in with it. The transfer curve simulation result of the VCO is shown in Fig. 3-15.

Fig. 3-15 Transfer curve of the VCO

3.3.5 Divider

The frequency of the input reference signal to the PFD is 125MHz but the VCO outputs four clock signals at 1GHz. A frequency divider is therefore needed to process the feedback signal to the PFD with a divided-by-eight circuit. The divided-by-two circuit is implemented as shown in Fig. 3-16 [15]. Then three divided-by-two circuits are cascaded to be a divided-by-eight circuit. The asynchronous counter has a bad property that it will accumulate the jitter stage by stage. As shown in Fig. 3-17, a synchronous counter is used at the last stage to re-sample the feedback signal, and it will eliminate the jitter accumulated at the asynchronous counters.

Fig. 3-16 Schematic of TSPC asynchronous divided-by-two circuit

Fig. 3-17 Divided-by-eight circuit with asynchronous and synchronous counters

3.4 PLL Liner Model

Although the PLL is a highly nonlinear system, it has been found that its transient behavior can be reasonably well approximated by a linear model when it is in lock and the phase and frequency changes of input signal are slow and minimal about their operating or bias point. A signal flow graph for the linear small signal model of the PLL is shown in Fig.

3-18.

Fig. 3-18 Linear model of the PLL

When the PLL is in lock, the PFD detects the phase difference between the input signal (θin) and the feedback signal (θback), defined as θe=θin-θback. The PFD produces UP and DOWN signals with different pulse widths which are proportional to θe. The CP is controlled by the UP and DOWN signals to offer a current signal. The average charge flowing into the LF is given by

2

p

avg e I

I θ

= π . The ratio of the current output over the input phase difference is defined as

2 Ip

π (A/rad). As the proposed equation in section 3.3.3, the LF has a transfer function F(s) (V/A). The ratio of the VCO oscillation frequency to the control voltage Vctrl is Kvco (Hz/V). Since , the transfer function of the VCO should be transformed to another type which is 2π K^vco

(rad/sec．V). Eventually, N is the divider ratio and the feedback factor is 1

N . The output frequency of the VCO will be N times the input reference frequency. Based on the above definitions and the PLL linear model, the loop gain of the PLL can be expressed as

( ) ( ) 1

The closed loop transfer function of the PLL can be found as

( ) ( ) ( )

From analysis of LF in section 3.3.3, the shunt capacitance C2 is typically much smaller than C1. Therefore, the influence of the capacitance C2 is neglected temporarily to simplify the equivalent system of the PLL. The characteristics of the transient response can be analyzed by a two-pole or second-order linear model of the PLL. With F(s) = R1 + (1/sC1), the closed loop transfer function of the PLL above can be expressed as

1 1 This can be compared with the classical two-pole system transfer function below

2 Then, the parameters such as natural frequency (ωn), zero of the LP (ωz) and the damping factor (ζ) can be derived as

1 The choice of the damping factor is a trade off between acquisition time and step response stability. If larger ζ is chosen, the system could have longer acquisition time. On the other hand, the system may be ringing for step response or become unstable with a smaller ζ.

3.5 Noise Analysis and Stability

The timing jitter could affect the maximum timing margin of the transmitter and the performance of the high speed serial link. The output jitter of the PLL is contributed by many different noise sources as shown in Fig. 3-19, where θin(s) is the reference noise, in(s) is the PFD and CP noise, Vn(s) is the LF noise and θn(s) is the VCO noise.

Fig. 3-19 The PLL linear model with different noise sources

Using the closed loop analysis, the transfer functions of different noise sources can be derived as

( ) = θ

^out

( )

s

=

N

×

K

_

( ) 2

The noise transfer functions have different characteristics. The Hin(s) and Hpdf_cp(s) are low pass functions, the HLF(s) is a band pass function and the Hvco(s) is a high pass function.

Based on the analysis, the loop bandwidth of the PLL should be maximized to meet the high pass function of the VCO to filter the timing jitter caused by the VCO. The maximum nature frequency ωn of the PLL is restricted to the input reference clock frequency ωin. Using the analysis from the PLL [16], the criteria of the stability limit can be derived as

2

3.6 Loop Parameter Design

The loop bandwidth and the phase margin are used to determine the component values of the LF. By substituting the equation (3-1) into the equation (3-9), the loop bandwidth can be described as From equation (3-15), the phase term will be determined based on the pole and zero of the loop filter such that the phase margin is calculated as

1 1

By setting the derivative of the phase margin equal to zero, the phase margin is the maximum when the loop bandwidth is set to the average of pole and zero.

z p From equation (3-2), the capacitance ration of C1 and C2 can be represented by

1 2

2

C 1

C = γ −

(3-25) The loop bandwidth can be written as

1 2

The design flow of a third-order PLL can be derived from equation (3-24), (3-25) and (3-26).Thus,the design flow can be summarized as follows：

(1) Determine the nominal value of N according to the input reference clock frequency and the output clock signals of the PLL.

(1) Determine the nominal value of N according to the input reference clock frequency and the output clock signals of the PLL.

在文檔中 2Gbps 低擺幅差動訊號傳輸之傳送器 (頁 31-0)