Transmitter Experimental Result

The transmitter is measured according to said environmental setup. Fig. 5-4 shows the differential output of the transmitter clock driver at VCO’s free running frequency 270 MHz.

In Fig. 5-5, the eye diagram of the transmitter data driver differential output at 540 Mbps (according to the Fig. 5-4). They indicate that the PRBS and Driver circuit can operate

normally. The random data are produced by the PRBS circuit build in the chip.

Fig. 5-4 the differential output of the transmitter clock driver at VCO’s free running frequency 270 MHz

at 540 Mbps (according to the Fig. 5-4)

In Fig. 5-6, the differential output of the transmitter clock driver at 533 MHz is shown.

Meanwhile, Fig. 5-7 shows the eye diagram of the transmitter data driver differential output at 1066 Mbps.

Fig. 5-6 the differential output of the transmitter clock driver at 533 MHz

Fig. 5-7 the eye diagram of the transmitter data driver differential output at 1066

Mbps

In Fig. 5-8 and 5-9, the transmitter operates at high frequency. The clock rate is 727 MHz and the data rate is 1454 Mbps.

Fig. 5-8 the differential output of the transmitter clock driver at 727 MHz

Fig. 5-9 the eye diagram of the transmitter data driver differential output at 1454

Mbps

The locked frequency of the PLL cannot be any higher in the normal design setup. Fig. 5-10 and Fig.5-11 show the experimental results of clock and data when the power supply voltage is turned to 4V.

Fig. 5-10 the differential outpus of the transmitter clock driver at 930 MHz when vdd = 4V

Fig. 5-11 the eye diagram of the transmitter data driver differential output at 1860

Mbps when vdd = 4V

Chapter 6

Conclusions and Future Work

6.1 Conclusion

To transmit high speed signals and achieve lower power consumption, a transmitter circuit with the RSDS^TM interface has been designed in this thesis. The chip is fabricated in a TSMC 0.35µm 2P4M CMOS process. The research results can be summarized as follows.

The transmitter is composed of a four-phase PLL, PRBS circuits, 2-1 multiplexers, an output clock driver and an output data driver with a pre-emphasis circuit. The input reference frequency of the four-phase PLL is 125MHz; it outputs four uniformly distributed clocks with 1 GHz frequency. The PLL comprises a Phase/Frequency Detector, a Charge Pump, a Loop Filter, a two-stage differential Voltage Control Oscillator and a divided-by-eight divider. The main issue of the PLL is to generate the required clock signals to the transmitter with timing jitter as small as possible. This may be down from system level to circuit level, including parameters design and layout considerations. Thus, the PLL outputs complementary clock signals to the multiplexers to convert parallel data to serial data. Finally, the output data driver drives the serial data onto the bus. Besides, the output clock driver drives the complementary clock signals onto another bus synchronously.

We have devoted to design a transmitter with the data rate at 2Gbps but the operation of the implemented chip can only achieve 1.4Gbps at most. Whole design issues and circuit operations are described in Chapter 3, 4 and the experimental results are shown in Chapter 5.

6.2 Future Work

The increasing demand for data bandwidth in communication systems has driven the development of high speed and low cost serial link technology. For the transmitter, the PLL output jitter must be reduced and the two-stage VCO must be designed carefully. The parasitic capacitors on the output nodes of the VCO and the noise effect by the large KVCO

should be also under consideration. Eventually, the output driver should be designed to reduce the increasing of additional data jitter of the transmitted data as far as possible.

References

[1] Craig Zajac; Sue Poniatowski; “A New Intra-Panel Interface for Large Size/ High Resolution TFT-LCD Applications,” Displays Division, National Semiconductor.

[2] National Semiconductor Corp., “RSDS^TM “Intra-panel” Interface Specification,”

Revision 1.0, May 2003.

[3] The Low-Voltage Differential Signal Applications, http://www.national.com/appinfo/interface/

[4] A. Lee; D.W. Lee; “Integrated TFT-LCD Timing Controllers With RSDS Column Driver Interface,” Interface Products, National Semiconductor Corporation.

[5] Andrea Boni; Andrea Pierazzi; Davide Vecchi; “LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35- µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, April 2001.

[6] National Semiconductor Application Note 1234, Craig Zajac; “RSDSTM Flat Panel Display Design Guidelines Part 1.”

[7] Y. Fouzar; Y. Savaria; M. Sawan; “A CMOS phase-locked loop with an auto-calibrated VCO,” Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on Volume 3, Page(s): III-177-III-180 vol.3, May 2002.

[8] Sungjoon Kim; Kyeongho Lee; Yongsam Moon; Deog-Kyoon Jeong; Yunho Choi;

Hyung Kyu Lim; “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” Solid-State Circuits, IEEE Journal of Volume 32, Issue 5, Page(s): 691 – 700,

May 1997.

[9] Jiren Yuan; Svensson, C.; “New TSPC Latches and Flipflops Minimizing Delay and Power,” VLSI Circuits, 1996. Digest of Technical Papers, 1996 Symposium on 13-15 June 1996 Page(s): 160 - 161

[10] Myoung-Su Lee; Tae-Sik Cheung; Woo-Young Choi; “A novel charge pump PLL with reduced jitter characteristics,” VLSI and CAD, 1999. ICVC '99. 6th International Conference on 26-27 Oct. 1999, Page(s): 596 – 598.

[11] Maneatis, J.G.; “Low-jitter process-independent DLL and PLL based on self-biased techniques,” Solid-State Circuits, IEEE Journal of Volume 31, Issue 11, Page(s):

1723 – 1732, Nov. 1996.

[12] Bautista, D.P.; Aranda, M.L.; “A low power and high speed CMOS Voltage-Controlled Ring Oscillator,” Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004

International Symposium on 23-26 May. 2004, Volume 4, Page(s): IV - 752-5.

[13] Yan, W.S.T.; Luong, H.C.; “A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator,” Analog and Digital Signal Processing, IEEE Transactions on Circuits and Systems II, Volume 48, Issue 2, Page(s): 216 – 221, Feb. 2001.

[14] Joonsuk Lee; Beomsup Kim; “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” Solid-State Circuits, IEEE Journal of Volume 35, Issue 8, Page(s):

1137 – 1145, Aug. 2000.

[15] Yuan, J.; Svensson, C.; “High-speed CMOS circuit technique,” Solid-State Circuits, IEEE Journal of Volume 24, Issue 1, Page(s): 62 – 70, Feb. 1989.

[16] Gardner, F.; “Charge-Pump Phase-Lock Loops,” Communications, IEEE Transactions on [legacy, pre - 1988] Volume 28, Issue 11, Page(s): 1849 – 1858, Nov. 1980.

[17] Linear Feedback Shift Registers

http://www.newwaveinstruments.com/resources/articles/m_sequence_linear_feedback_

shift_register_lfsr.htm

VITA

鄭鍵樺於西元 1981 年 10 月 11 日出生於彰化縣溪湖鎮，性別男。西元 2003 年畢 業於國立交通大學電子工程學系，獲學士學位，西元 2005 年畢業於國立交通大學電子 研究所，獲電機資訊學院碩士學位。

主修學科

數位積體電路 柯明道 教授

類比積體電路 I 吳介琮 教授

類比積體電路 II 吳重雨 教授

積體電路設計實驗 I 李鎮宜 教授

積體電路設計實驗 II 李鎮宜 教授

積體電路之靜電防護設計特論 柯明道 教授

計算機輔助設計特論 周景揚 教授

生物導論 黃鎮剛 教授

個人通訊 林一平 教授

Email : [email protected]