Thesis Organization

This thesis consists of six chapters including the present chapter. Chapter 2 describes the background about the research of this thesis. It starts with the RSDS^TM specification and brings out the considerations of the high speed serial link design. In chapter 3, the architecture and block circuits of the PLL which are the main portion of the transmitter are described clearly. Chapter 4 shows the whole architecture of the transmitter including the simulation results. The layout implementation and the measurement results of the

transmitter are given in Chapter 5. Finally, Chapter 6 summaries this work, draws a conclusion and discusses the future development about this thesis.

Chapter 2 Background

2.1 RSDS ^TM Specification [2]

2.1.1 Scope

RSDS^TM, Reduced Swing Differential Signaling, is an intra-panel interface bus standard. The RSDS^TM standard defines the characteristics of transmitter and receiver along with the protocol for a chip-to-chip interface. The RSDS^TM interface standard is intended to cover electrical characteristics and protocol of the data only. Additional Control signals that are required by the Source (Column) Driver and/or Gate (Row) Drivers are not covered in this specification, as they are unique to the specific LCD manufacturer’s design.

2.1.2 Introduction of RSDS

The RSDS^TM bus provides many benefits to the applications that include the following：

z Reduced bus width – enables smaller and thinner column driver boards

z Low EMI generation – eliminates EMI suppression components and shielding z High noise rejection – maintains signal image

z High throughput – enables high resolution display

The RSDS^TM interface is intended to be used in display applications with resolutions between VGA through UXGA or higher. Higher resolution support is scaleable with RSDS^TM and is only limited by the RSDS^TM bus bandwidth supported by the transmitter/receiver pair.

2.1.3 System Diagram

Fig. 2-1 depicts a typical application block diagram of the LCD Module. The RSDS^TM bus is located between the Panel Timing Controller and the Column Drivers. There are several connection schemes allowed which are discussed in the bus configuration section.

This bus is typically nine pair wide for 6bit/color plus clock and is a multi-drop bus configuration, 1 transmitter and multiple receivers.

Fig. 2-1 Block Diagram of the LCD Module with Discrete Timing Controller

2.1.4 Electrical Specification

A typical RSDS^TM interface circuit is shown in Fig. 2-2. The circuit contains three parts：a transmitter (TX), receivers (RX) and a balanced interconnecting medium with termination.

Fig. 2-2 RSDS^TM Interface

2.1.5 RSDS

Transmitter Characteristic

The Driver output consists of two complimentary outputs that are terminated at the end of the Data Bus. A differential voltage is generated from two single-ended outputs of the transmitter. As in LVDS, the single-ended outputs alternate between sourcing and sinking of a constant current. The differential voltage is the product of this constant current across the terminating resistance RL as shown in Fig. 2-3.

Fig. 2-3 RSDS^TM reference circuit and transmitter output

Due to a wide variation in the characteristic impedance of the transmission media (25Ω to 100Ω), it is recommended that the transmitter be designed with the capability to drive such loads with a minimal amount of signal integrity artifacts such as reflection, ringing,

overshoot, undershoot.

The following specifications (see Table 2-1) apply to both clock and data pairs over a specified range of termination resistance values and operating voltages.

Table 2-1 Electrical Specifications of RSDS^TM transmitters

2.1.6 Bus Configuration

The RSDS^TM is a versatile interface that may be configured differently depending upon the end application requirements. Considerations include the location of the TCON, the resolution of the panel, and the color depth for example. The common implementations include the following bus types：

z Type 1 – Multi-drop bus width double terminations (shown in Fig. 2-4)

In a Type 1 configuration, the source (TCON) is located in the center of the bus via a short stub. The bus is terminated at both ends with a nominal termination of 100 Ω. The interconnecting media is a balanced coupled pair with ideal (unloaded) differential impedance of 100Ω. However in actual applications the bus impedance can be much lower than ideal due to the additional loading or PCB characteristics. The number of RSDS^TM data pairs is 9 or 12 depending upon the color depth supported. In this application, the RSDS^TM

driver will see a DC load of 50Ω instead of 100Ω. In this case, the output drive of the RSDS^TM driver must be adjusted to comply with the VOD specification with the 50Ω load presented in the type 1 configuration.

Fig. 2-4 Type 1 Bus Configuration

z Type 2 – Multi-drop bus with single end termination (shown in Fig. 2-5)

In a Type 2 configuration, the source (TCON) is located at one end of the bus. The bus is terminated at the far end with a nominal termination of 100Ω. The interconnecting media is a balanced coupled pair with nominal (unloaded) differential impedance of 100Ω. The bus may be a single or dual bus depending upon the panel’s resolution. The number of RSDS^TM data pairs is 9 or 12 depending upon the color depth supported for a single bus.

Fig. 2-5 Type 2 Bus Configuration

z Type 3 – Double multi-drop bus with single termination (shown in Fig. 2-6)

In a Type 3 configuration, the source (TCON) is located in the center of the application.

There are two buses out of the TCON that run to the right and left respectively. Each bus is

a balanced coupled pair with nominal (unloaded) differential impedance of 100Ω. The number of RSDS^TM data pairs is 9 or 12 depending upon the color depth supported for a single bus for each bus. Note that the connection of the TCON to the main line is not a stub in this configuration, but rather a part of the main line. This helps to improve signal quality.

Fig. 2-6 Type 3 Bus Configuration

Note that in Fig. 2-4, 2-5 and 2-6, the complete bus is not illustrated; only a single RSDS^TM pair is shown. The number of column drivers on the bus is also application specific and depends upon the panel resolution and also if a single or dual bus is used.

2.2 Basic Link Design

A general serial link is composed of three primary components：a transmitter, channels, and a receiver, as shown in Fig. 2-7. The data before transmission are usually arranged in parallel form in order to increase the bandwidth of the link. The transmitter has to convert the parallel data into serial stream before the output driver drives signals onto the channels.

RSDS^TM uses differential data transmission to deliver the serial data stream and the transmitter is configured as a switched-polarity current generator. A differential load resister at the receiver end provides current-to-voltage conversion. For operation in the Gbps range, an additional termination resistor is usually placed at the source (transmitter) end to

suppress reflected waves caused by crosstalk or by imperfect termination, due to package parasitic effect and component tolerance. Moreover, RSDS^TM uses a lower voltage swing to achieve further advantages in terms of reduced crosstalk and radiated EMI. Therefore, the double termination scheme is used and the termination resistors are integrated in the transmitter (RT-T) and in the receiver cell (RT-R) [5].

Fig. 2-7 Block diagram of the basic serial link

After the data are transmitted onto the channels successfully, the receiver amplifies and samples the received bit stream. The clock recovery circuit restores the clock of transmitter by detecting the transition edge of received data. Eventually, the receiver gets back the correct data by sampling the center point of the received bit stream at each transition edge of the recovered clock.

2.3 Interface Consideration

The RSDS^TM bus can provide reliable, low power, low EMI data transmission at rates that exceed the requirements of XGA system with a 75Hz refresh rate. In order to build the most robust RSDS^TM interface, certain precautions need to be taken. There are three main considerations for an RSDS^TM based application[6]：

z RSDS^TM Bus Configuration

For XGA and SXGA panels, there are three types of RSDS^TM bus configurations, which are outlined in section 2.1.6. All of the bus configurations should be implemented in 50 Ω transmission lines. Each of them requires slightly different terminations and supply currents. Therefore, choosing the appropriate bus configuration is critical to a good system design.

z RSDS^TM Layout

In general, a RSDS^TM bus should be routed and laid-out with the same consideration as any high speed differential bus. The following are some of the basic high speed differential routing principles：

- Positive and negative traces of a differential pair should be the same length and routing as close together as possible

- Spacing between differential pairs should be double the spacing within a differential pair

- Changing layers along the bus should be minimized - The number of vias attached to a bus should be minimized

- The bus should be electrically separated from other dynamic signals to minimize noise and crosstalk

- Forty-five degree angles should be used instead of right angles when changing the bus direction

z RSDS^TM Bus Termination

The generalizations used are not exactly accurate and there will still be some inefficiency in the termination scheme. The error is caused by the fact that the RSDS^TM bus is loaded with connections to 8 or 10 column drivers, each of which can be approximated by

a capacitive load on the bus line (typically 2-5pF per connection). Fig. 2-8 shows an example with the column driver capacitive loading included. The net result of the capacitive loading is to decrease the effective impedance of the traces. In order to better match the reduced impedance, the termination resistor may have to be lowered. Empirical evidence indicates that the termination resistor should be around 70 Ω in order to provide the best impedance that matches the differential traces.

Fig. 2-8 Loading of RSDS Bus [6]

2.4 Eye Diagram

A transmitter delivers signals based on a kind of selected interface specification. When long stream bits of data are conveyed, it is inefficient and non-smart to check the bits one by one. Therefore, an eye diagram is made to understand the characteristics of transmitted bits conveniently.

An eye diagram of a signal overlays the signal’s waveform over many cycles. Each cycle’s waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. The vertical thickness of the line bunches in an eye diagram indicates the

magnitude of AC voltage noise; whereas the horizontal thickness of the line bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen. The size of the eye opening in the center of an eye diagram indicates the amount of voltage and timing margin available to sample this signal. Thus, for a particular electrical interface, a fixed reticule or window could be placed over the eye diagram showing how the actual signal compares to minimum criteria window, know as the eye mask. If a margin rectangle with width equal to the required timing margin and height equal to the required voltage margin fits into the opening, then the signal has adequate margins.

Chapter 3

Phase-Locked Loop

3.1 Introduction

Phase-locked loops (PLL) are analog building blocks used extensively in many analog, digital and communication systems. Their use has become attractive for many applications such as clock recovery, frequency synthesizers, FM demodulators and others. These are only few applicable areas, but PLL has undoubtedly become an important building block in many electronic systems. Recently, as the needs for high speed data transmissions rise, the PLL technique plays a key role to implement the demand. In this chapter we first explore the architecture of the PLL, and then explain the circuit implementations for the PLL to achieve the clock rate at 1GHz. In this transmitter, we need a pair of complementary clock signals with 1GHz frequency to trigger the output driver. The detailed discussion of the transmitter operation will be shown in next chapter. The linear model, the noise and the stability are all taken into consideration in 3.4 and 3.5, followed by a section discussing the flow of design and the way to make proper decision on loop parameters of the PLL. The simulation results are presented in the final section of this chapter.

3.2 Architecture of PLL

Fig. 3-1 shows a block diagram of the basic PLL system. The system consists of a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider. The VCO is simply an oscillator whose frequency is proportional to an externally applied voltage. Before inputting the clock at reference frequency (Ref_CLK), the VCO oscillates at its free-running frequency. When the Ref_CLK signal is input, the phase/frequency detector detects both the Ref_CLK and the feedback signal (Fb_CLK). Afterward the detector and the charge pump produce a dc or low frequency signal proportional to the phase difference between Ref_CLK and Fb_CLK. The loop filter acts as a low pass filter and is used to extract the average value from the output of the charge pump. This signal is then amplified and used to drive the VCO. The VCO’s oscillation frequency will be changed by the control voltage (Vctrl) according to the reference frequency. A frequency divider being used in the diagram, the output clock’s frequency of the VCO will be N times of the Ref_CLK signal. When the loop is locked, the negative feedback of the loop results in the output of the VCO being synchronized with the input signal. Moreover, the input signal (Fref) and the feedback signal (Fb) are phase-aligned. The PLL turns out to be able to lock to the input signal successfully.

Fig. 3-1 Functional block diagram of charge pump PLL

3.3 Circuit Implementation

3.3.1 Phase/Frequency Detector

The phase/frequency detector (PFD) is a digital sequential circuit built based on a tri-state operation. It is used to detect the phase difference between the reference (Ref_CLK) and the feedback (Fb_CLK) signals. Fig. 3-2 shows the implementation of PFD [7][8]. The PFD is composed of two high speed TSPC (True-Single-Phase-Clocking [9]) D-flip flops, a NOR gate, inverters and a buffer in the reset path.

Fig. 3-2 Phase/Frequency detector with TSPC D-flip flops

The PFD is triggered by the positive edges of the Ref_CLK and the Fb_CLK. It detects the phase difference between them and outputs two signals, UP and DOWN, to represent the phase relationship of them as shown in Fig.3-3. If the Ref_CLK and the Fb_CLK are in

phase, the output waveforms of UP and DOWN will be the same. The controlled voltage and the oscillation frequency of the VCO remain invariable.

Fig. 3-3 Operation of PFD

When the Fb_CLK lags the Ref_CLK, the UP signal will be switched from low to high first. This will in turn increase the frequency of the VCO and the Fb_CLK signal. Then the positive edge of the Fb_CLK arrives and the DOWN signal will be switched from low to high, too. When both UP and DOWN signals are set at high, the reset signal will thus be turned to high in order to reset them to low. The comparison between Ref_CLK and Fb_CLK in this cycle is finished. In contrast, if the Fb_CLK leads the Ref_CLK, the output signals, UP and DOWN, of PFD will be used to decrease the frequency of the VCO and the Fb_CLK signal. This type of operation has a linear range of ±２ and can act as both a π phase detector and a frequency detector. This property will greatly enhance the locking range.

A low precision PFD has a wide dead zone as shown in Fig. 3-4, which results in increased jitter. Ideally, the PFD should have the ability to distinguish any phase error between Ref_CLK and Fb_CLK. The dead zone will occur in practical exercises when the loop is in a lock mode and the PFD cannot detect the small phase difference of Ref_CLK and Fb_CLK. The detected phase error will thus remain zero and this will result in an increase of unavoidable jitter of the PLL.

Fig. 3-4 The PFD dead zone

The delay buffer in the reset path is used to avoid the occurrence of dead zone. For in-phase inputs of Ref_CLK and Fb_CLK, the charge pump will see both UP and DOWN pulses for the same short period of time. If there is a phase difference between Ref_CLK and Fb_CLK, the width of UP and DOWN pulses will be proportional to the phase difference of the inputs. Fig.3-5 shows the SPICE simulation result of the proposed PFD circuit.

Phase Difference between Ref_CLK and Fb_CLK (ps)

UP pulse width - DOWNB pulse width (ps)

Fig. 3-5 simulation result of PFD without dead zone

3.3.2 Charge Pump

The charge pump (CP) cooperates with the PFD to change the control voltage of the VCO. The circuit implementation of the charge pump is shown in Fig. 3-6 [10]. It can charge and discharge the capacitance of the loop filter to vary the Vctrl according to UP and DOWNB signals from the PFD. There are some problems in conventional charge pump circuits such as charge injection and clock feed through. These problems will result in a phase offset at the input of the PFD when the PLL is locked. In order to overcome these problems, the two switch devices are separated from the output voltage. Therefore, the output voltage is now isolated from the switching noise resulting from the overlap capacitance of the two switch devices. In addition, the intermediate node between the current source and switch devices will charge to the output voltage only by the gate overdrive of the current source devices, Vgs –Vt, an amount independent of the output voltage. The charge pump circuit can therefore control Vctrl and successfully reduce the static phase offset.

Fig. 3-6 Schematic of the charge pump

3.3.3 Loop Filter

The loop filter (LF) is a low pass filter used to extract the average value from the charge pump output. The schematic of the loop filter is shown in Fig. 3-7. It is usually composed of a resistor R1 in series with capacitor C1 and a capacitor C2 in parallel.

Fig. 3-7 Schematic of the loop filter

The loop filter provides a pole in the origin to provide an infinite DC gain so as to minimize the static phase error. The resistor R1 and capacitance C1 provide a zero in the open loop response in order to improve the phase margin to ensure overall stability of the loop. Finally, the use of the capacitance C2 is to reduce the ripple noise on Vctrl to mitigate the frequency jump. The transfer function of the loop filter can be expressed as

( )

The use of the capacitance C2 will make the overall PLL system third-order and affect the stability of the loop. In general, when the capacitance C2 is much smaller than C1, the third-order loop can be approximated to a second-order one.

3.3.4 Voltage Controlled Oscillator

The building blocks of the VCO include a replica-feedback current source bias circuit, a two-stage ring oscillator, differential-to-single-ended converter circuits and duty-cycle corrector circuits as shown below.

Fig. 3-8 Architecture of the VCO

The VCO is eventually designed to produce four full swing clock signals, F0~F3, at 1GHz frequency. In order to achieve low jitter operation, the circuit should have low power and

The VCO is eventually designed to produce four full swing clock signals, F0~F3, at 1GHz frequency. In order to achieve low jitter operation, the circuit should have low power and