CHAPTER 4 HC-TFTs UNDER AC STRESS
5.2 Future Work
In addition to the hot-carrier degradations in p-channel poly-Si TFTs, negative bias
temperature instability (NBTI) is another key reliability issue that is of immediate concern for practical applications of p-channel poly-Si TFTs. Unfortunately, few efforts are done for investigating the mixed effects of hot-carrier effect and NBTI. This topic is thus important and in the future, and the HC-TFT should be a useful test vehicle for this purpose. It should be also capable of identifying the degradation mechanism in different parts of the channel under various HC/NBTI stress conditions.
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Fig. 2-1 Cross-sectional view of the test device.
Fig. 2-2 Top view of HC-TFTs device.
Fig. 2-3 Definition of (a) test transistor (TT) and (b) monitor transistors (MTs).
Fig. 2-4 Illustration of the major damage region in the HC-TFTs under severe HC stress condition.
Fig. 2-5 Definition of “Normal mode” and “Reverse mode” of (a) Short-DMT and (b) test transistor.
Fig. 3-1 Schematic illustration of defect types and their creation in the p-channel device caused by hot carriers.
Fig. 3-2 Subthreshold characteristics of (a) normal mode and (b) reverse mode of the test transistor before and after lower DC stress at VG/VD of -7.5 V/-20 V for 1000 sec
Fig. 3-3 Subthreshold characteristics of (a)SMT, (b)CMT, (c)DMT and (d)Short DMT transistors contained in the same test structure characterized in Fig. 3-2 before and after mild DC stress at VG/VD of -7.5 V/-20 V for 1000 sec.
Fig. 3-4 Schematic illustrations of (a)BTBT occurring in the drain and (b)suppression of the BTBT after stress due to electron trapping in the oxide.
Fig. 3-5 On-current degradation of test structures under VD of -20 V and various VG for 1000 sec.
Fig. 3-6 Subthreshold characteristics of (a) normal mode and (b) reverse mode of a test transistor before and after higher DC stress at VG/VD of -7.5 V/-25 V for 1000 sec.
Fig. 3-7 Energy band diagrams under different measurement configurations.
Fig. 3-8 Subthreshold characteristics of (a)SMT, (b)CMT and (c)DMT transistors contained in the same test structure characterized in Fig. 3-8 before and after higher DC stress at VG/VD of -7.5 V/-20 V for 1000 sec.
Fig. 3-9 Subthreshold characteristics of (a) normal mode and (b) reverse mode of the Short DMT before and after higher DC stress at VG/VD of -7.5 V/-25 V for 1000 sec
Fig. 3-10 On-current degradation of TT and different MTs as a function of stress VD with VG= -7.5 V for 1000 sec.
Fig. 3-11 Threshold voltage shifts of the test structure under VG of -7.5 V and various VD for 1000 sec.
Fig. 3-12 The on-current degradation of TT and different MTs as a function of stress VG with VD= -25 V for 1000 sec.
Fig. 3-13 Threshold voltage shift of the test structure under VD of -25 V and various VG for 1000 sec.
Fig. 3-14 Schematic illustration of electrons trapped in the gate oxide under high vertical electric field.
Fig.3-15 The distribution of potential and electric field at space charge region.
Fig. 4-1 (a) Major parameters in the AC signal train. (b) AC stress configuration.
Fig. 4-2 Subthreshold characteristics of TT under (a) normal- and (b) reverse-mode of measurements before and after the AC stressing under VG_low/VD=-10 V/-25 V, freq.=500 kHz, tr=tf=100 ns and total t low=500 sec.
Fig. 4-3 Subthreshold characteristics of (a) SMT, (b) CMT, (c) DMT and short-DMT transistors in a test structure before and after the AC stressing under VG_low/VD=-10 V/-25 V, freq.=500 kHz, tr=tf=100 ns and total t low=500 sec.
Fig. 4-4 Subthreshold characteristics of a TT before and after AC stress for 500 sec with the frequency of (a) 100 kHz and (b) 1 MHz.
Fig. 4-5 Subthreshold characteristics before and after AC stress for 500 sec with the frequency of (a) 100 kHz and (b) 1 MHz for DMT, and (c) 100 kHz and (d) 1 MHz for
short-DMT.
Fig. 4-6 On-current degradation as a function of frequency under AC stress.
Fig. 4-7 Threshold voltage shift as a function of frequency under AC stress.
Fig. 4-8 Subthreshold characteristics before and after AC stress for 500 sec with the rising time of (a) 100 ns and (b) 10 ns for TT.
Fig. 4-9 Subthreshold characteristics before and after AC stress for 500 sec with the rising time of (a) 100 ns and (b) 10 ns for DMT, and (c) 100 ns and (d) 10 ns for
short-DMT.
Fig. 4-10 On-current degradation as a function of rising time under AC stress.
Fig. 4-11 Threshold voltage shift as a function of rising time under AC stress.
Fig. 4-12 Degradation mechanism of variable rising time under AC stress.
Fig. 4-13 Subthreshold characteristics before and after AC stress for 500 sec with the falling time of (a) 100 ns and (b) 10 ns for TT.
Fig. 4-14 Subthreshold characteristics before and after AC stress for 500 sec with the falling time of (a) 100 ns and (b) 10 ns for DMT, and (c) 100 ns and (d) 10 ns for
short-DMT.
Fig. 4-15 On-current degradation as a function of falling time under AC stress.
Fig. 4-16 Threshold voltage shift as a function of falling time under AC stress.
Fig. 4-17 Degradation mechanism of variable falling time under AC stress.
Fig. 4-18 Subthreshold characteristics of TT before stressing.
作者簡介
A Study of P-Channel Poly-Si TFT Degradation under Hot-Carrier Stress Using a Novel Test Structure