LTPS TFTs are an important technology in industrial applications. In order to further advance the technology and extend its application scope, significant improvement in reliability of LTPS TFTs is essential. Therefore, the understanding of reliability mechanisms becomes more and more important. Moreover, CMOS technology is necessary for driving circuits, which means that the task of reliability investigation is not only restricted to n-channel LTPS TFTs but also apply to p-channel ones. In this regard, the hot-carrier effects and associated mechanisms of n-channel LTPS TFTs under either DC (static) or AC (dynamic) stress have been widely explored and discussed [24] [27]-[33]. However, few efforts are done to p-channel LTPS TFTs to this date.
As mentioned above, hot carriers are generated during normal device operation by the high-electric field presenting near the drain side. Charges trapped into the gate oxide and interface trap generation may occur and lead to device degradation. In contrast to the MOSFETs, the situation becomes even more complicated for poly-Si TFTs due to the lack of substrate contact in typical device configuration, as well as the large amount of potential defect sites existing at the grain boundaries in the channel. In the past, a lot of research
efforts have been made to study the degradation mechanism of static hot-carrier operation [34]-[38]. The results indicated that the damage regions could be situated in local regions of the channel which can be predicted using simulation and probed using measurement techniques [39] [40]. However, all of these existing techniques cannot directly resolve the location-dependent damage characteristics. Concurrently, in recent years, many works have investigated the degradation mechanisms of dynamic hot-carrier operation [29]-[33]. The situation becomes more complicated than that during static operation since the degradation is related to the different stages of the AC stress signal. It is still difficult to resolve and understand the detailed mechanisms responsible for the damage induced in different parts of the channel of the stressed device.
In this study, we use a novel test structure which was proposed by our group previously [41] [42] to study the hot-carrier effects of p-channel LTPS TFTs. The unique tester, which is introduced in Chapter 2, is designed for spatially resolving the non-uniform damage induced by hot-carriers. With such capability, it was employed in this thesis to investigate the hot-carrier degradation caused by either DC (static) or AC (dynamic) stress tests for p-channel LTPS TFTs. The characteristics of such structure under various stress conditions including the gate and drain voltages, stressing time, frequency and falling/rising time, were characterized and discussed to verify the degradation mechanisms under DC/AC stress.
1.4 Thesis Organization
The thesis is split into five chapters. After a brief introduction of LTPS TFTs, the reliability issues, and the motivation of this study given in this chapter, we describe the device structure of the novel tester, dubbed as HC-TFTs, and the fabrication process in Chapter 2.
This chapter also contains the description of the DC/AC stress measurement system setup and measurement scheme.
In Chapter 3, the novel HC-TFT devices are used to analyze related reliability issues.
We observe the influence of several DC (static) stress conditions on the test structure and discuss the results and explain the degradation mechanisms.
In Chapter 4, we present the results of the AC stress measurements. Analysis of the electrical characteristics of the test structure under different AC stress conditions is given.
Effects of stress configurations and the AC stress conditions, including frequency and transient stages are also explored and addressed.
Finally, we summarize the conclusion and suggest future work in Chapter 5.
Chapter 2
Device Fabrication and Measurement Schemes
2.1 Device Fabrication and Operating Principles of HC-TFTs
Figure 2-1 shows a cross-section of the test structure. First, a 100nm-thick thermal oxide was grown in a furnace on 6-inch silicon wafers to simulate the glass substrate. Then, a 100nm thick a-Si layer was deposited as active layer by a low pressure chemical vapor deposition (LPCVD) system at 550 ℃. Next, the a-Si was crystallized into poly-Si by solid phase crystallization (SPC) annealing step performed at 600 ℃ for 24hr in N2 ambient.
Afterwards, the wafers were subjected to photolithography and etching steps for the definition of active region. A 30nm-thick TEOS-oxide layer and a 150nm-thick poly-Si layer were then subsequently deposited by LPCVD system, followed by the patterning of the poly-Si layer to serve as the gate electrode. Subsequently, a self-aligned ion implantation was used to form p+ gate and p+ source/drain simultaneously with BF2+ ions for p-channel TFTs. The implant energy was 50 keV with a dose of 5×1015 cm-2. A LPCVD oxide layer of 200 nm was used as the passivation layer to prevent the penetration of humidity and impurity, followed by contact-hole formation. After the metallization step, the test structure further received a plasma treatment in NH3 ambient at 300 ℃ in order to reduce the structural defects and improve devices performance.
The top view of the HC-TFTs test structure is shown in Fig. 2-2. It can be seen that the
test structure is configured with four pairs of p+ electrodes at the edges of the channel. In the x- (i.e., horizontal)-direction as shown in Fig. 2-3a, the device consisting of one pair of p+ regions alongside the lateral channel is called the “test transistor (TT)”, which will be subjected to the hot-carrier stress by applying a high voltage to its drain for inducing the HC degradations. In the y-(i.e., vertical)-direction as shown in Fig. 2-3b, the other three pairs of p+ regions and the channel regions form the three transistors called “monitor transistor (MTs)”, which are used to observe the degradation incurred at different regions of the test transistor channel after hot-carrier stress. In other words, the current–voltage (I–V) characteristics of the MTs could be characterized before and after the HC test to study the extent and evolution of degradation. The p+ poly-gate covering the whole channel region serves as the common gate for TT and all three MTs. In Fig.2-3b, according to their relative position in the channel of the test structure, the three MTs are denoted as SMT (i.e., source-side MT), CMT (i.e., central MT), and DMT (i.e., drain-side MT). This unique configuration allows us to investigate the damage locations, and identify the associated mechanisms at different locations along the channel of the test transistor after stressing.
Furthermore, in order to prevent dopant diffusion from the drain (source) of the TT to the channel region of DMT (SMT) which may lead to failure of the MT, the mask has been designed with an offset region which is located between the DMT (SMT) and the drain (source) of the TT. However, this design raises an issue that the MTs would be blind to detect the degradation induced in the offset region (see Fig. 2-4). The offset region near drain of the TT is expected to be the main damage region, because it is supposed to receive the highest electrical field during hot-carrier stress. To address this issue, one method was proposed [43]. The method is to change the current path of measurement, as shown in Fig.
2-5 (a), in which one p+ region of the DMT and the drain of the TT are treated as the “source”
and “drain” terminals in the measurements. Such characterization scheme is dubbed as
“short-DMT” measurements in this work. Executing this method can help sense the damage characteristics in the offset region clearly.
Figures 2-5 (a) and (b) specify the “normal’ and “reverse” modes of TT and short-DMT measurements. In normal measurements, the nominal gate and drain are negatively biased with respect to the nominal source (which is set to ground). In order to analyze devices in details, reverse measurements that have the nominal gate and source negatively biased with respect to drain (which is set at ground) are also executed and are denoted as “Reverse short-DMT” and “Reverse TT”, as shown in Fig. 2-5.
2.2 Measurement Schemes
Normal experimental procedure carried out in this work is to perform various DC/AC hot-carrier stress on the TT first, then the characteristics (e.g., IDS - VGS) of the TT and MTs before and after hot-carrier stress were measured and analyzed.
Execution of DC stress and measurements of the subthreshold and output characteristics of the test devices were done by a Keithley 4200 semiconductor characterization system with Keithley Interactive Test Environment (KITE) software. AC stress and measurements were performed using Keithley pulse generator 4200-PG2 in the same system. Temperature- regulated hot chuck was used to control and fix the temperature of the wafers at 30 ℃ during both DC and AC stress periods.
2.3 Definition and Extraction of Device Parameters
The threshold voltage of MTs is defined as the value of VGS when the drain-current (IDS) equals
L nA×W
10 at VDS of -0.1V, where W and L are channel width and channel length, respectively. The extracted value with this method is donated as “Vth”. Besides, due to the
large number of defects generated in the channel during the stress, the threshold voltage of TT is strongly influenced by the severe degradation of subthreshold swing. In line with this, Vth
of TT is redefined as VGS when IDS equals
L nA×W
1 at VDS of -0.1V. This method is adopted in most studies on the HC reliability of poly-Si TFTs because of its simplicity in measurement. Moreover, the definition of ΔVth is defined in the following equations:
ΔVth = Vth,stress – Vth,fresh (Eq. 2-1).
where Vth,fresh and Vth,stress are the threshold voltage before and after stressing, respectively.
Furthermore, the degradation of on-current is a useful indicator for observing the characteristics of device under hot-carrier stress. In this work, from the measured IDS-VGS
curve at VDS = -0.1V, the on-current is extracted at VGS - ΔVth = -15V. The degradation (%) of the on-current is defined as ( ΔIon / Ion,fresh ) × 100% , where ΔIon = ( Ion,stress - Ion,fresh ), Ion,fresh is the initial on-current (i.e., fresh condition), and Ion,stress is the on-current after stressing.
Chapter 3
HC-TFTs under DC stress
3.1 DC Stress Conditions
In this chapter, the static stress is used to degrade the HC-TFTs for the evaluation of the HC effects. In addition to recording the shift of electrical parameters of the test transistor, electrical characteristics of the monitor transistors embedded in the same test structure are also analyzed, which are extremely useful for understanding of the degradation induced in different parts of the channel. The basic parameters of DC signals consist of gate voltage (VG), drain voltage (VD), source voltage (VS), and stress time. Throughout this work the source was fixed at ground the temperature of test environment was kept at 30 ℃. The total stress time is 1000 sec unless it is specified otherwise. Different combinations of VG and VD
were chosen to investigate the degradation of HC-TFTs under hot-carrier DC stress.
3.2 Degradation Mechanisms of p-channel Poly-Si TFTs under Static Stress
Figure 3-1 depicts the hot-carrier degradation mechanisms of p-channel poly-Si TFTs under DC stress. As the absolute magnitude of the drain bias is high, holes can obtain energy from the high electric field in the drain junction and become “hot carriers”, which would cause impact ionization and lead to the generation of electron-hole pairs. The hot carriers may release their energy inside the channel or near channel/oxide interface, thus additional defects and interface states are thus created. These generated defects and
interface states would degrade the subthershold swing and mobility of the device and cause the on-current degradation. Moreover, portions of the hot electrons generated by impact ionization would surmount the barrier height at the oxide interface and inject into the gate oxide. Trapping of the electrons shifts the device’s threshold voltage. Injection efficiency depends on the strength of the vertical electric field at the injection spot.
3.3 HC Stress under Mild Stress Bias
Typical subthreshold characteristics of the lateral test transistor before and after DC stress are shown in Fig. 3-2. The test transistor was stressed with VG = -7.5 V and VD = -20 V for 1000 sec. The ID-VG curve shows only a negligible shift after stressing under the above-specified mild stress condition. In the figures the only noticeable change is the off-state leakage current under normal mode which will be addressed later. Thus the information provided by the conventional test transistor is unclear and insufficient, so we do not know details about the major damage location in the stressed channel [37] [38], nor the degradation mechanisms. Therefore, the subthreshold characteristics of different independent monitor transistors (MTs) in the test structure are also measured to resolve these deficiencies, and the results are shown in Fig. 3-3.
As compared with the characteristics of TT under reverse-mode measurements shown in Fig.3-2 (b), it can be seen that the off-state leakage current of normal mode is reduced and becomes independent of the gate bias after hot-carrier stress, as shown in Fig.3-2 (a). This phenomenon can be explained by the band diagrams illustrated in Fig.3-4. In Fig. 3-4 (a), due to the strong electric field in the drain near the oxide interface, the field emission of conduction holes leaving the electrons to cause the band-to-band tunneling (BTBT) current.
When the device was stressed under hot-carrier condition, portions of the electrons generated by impact ionization are trapped in the gate oxide near the drain side as mentioned in last
section, so the electric field is reduced and the BTBT current is suppressed, as shown in Fig.
3-4(b). Note that the reduction of off-state leakage after hot-carrier stress was not observed in n-channel poly-TFTs [41] [42]. This is attributed to the smaller effective mass as well as the smaller energy barrier height at Si/SiO2 interface for electrons, compared with the holes, so hole trapping is less likely to occur in the case of n-channel devices.
The subthreshold characteristics of different MTs embedded in the same test structure studied in Fig. 3-2 are shown in Fig. 3-3. It can be seen that no visible damage occurs in the SMT and CMT. However, the DMT and short-DMT show significantly degraded on-current and positive shift in threshold voltage. This proves the above statements about the trapping of electrons in the oxide near the drain side of the TT.
Fig. 3-5 shows the degradation of on-current of TT and all MTs as a function of stress VG
with VD = -20 V for 1000 sec. The results indicate that the degradation trend of TT is followed by that of DMT and short-DMT, pinpointing the location where major damage is induced. Moreover, both DMT and short-DMT exhibit higher degradation than the TT, especially the latter one. This demonstrates the high sensitivity of the test structure in resolving the location–dependent damage characteristics.
3.4 HC Stress under Severe Stress Bias
In Fig. 3-6, the test transistor was stressed under a hot-carrier stress biases of VG = -7.5 V and VD = -25 V, much severe than that executed in the previous section, for 1000 sec. As expected, the resultant degradations in the device characteristics in terms of increased subthershold slope and reduced on-current are much bigger than those under mild stress shown in Fig. 3-2. In Figure 3-6(a), relative to the post-stress ID-VG curve which was measured at high absolute drain bias of VD=-3 V, the shift of ID-VG curve after hot-carrier DC stress is more significant when the lateral test transistor was measured at low absolute drain
bias of VD=-0.1 V. This represents an evidence that most of the damage events occur in the channel near the drain side of the test transistor [44]. Hot-carrier stress can generate extra interface states and/or grain-boundary defects, and form a defect-rich and resistive region in the channel near the drain side [45]. As a larger absolute magnitude of drain bias is applied during the measurements of transfer characteristics, the depletion region near the drain side extends more deeply into the channel and effectively screens out the defects induced in the region, thus relieving the post-stress ID–VG shift. In contrast, the subthreshold characteristics of TT under reverse-mode shown in Fig. 3-6(b) show clear shift after stress regardless of the drain bias (-0.1 or -3 V). Under such mode of measurements the damaged region which contributes a high resistance is close to the source side and cannot be screened out by the drain bias. The situation can be schematically illustrated in Figure 3-7 [46].
Damage induced by hot carriers can form a potential energy hump near the nominal drain side of the TT, as shown in Fig. 3-7 (a). A high absolute drain bias tends to drop the energy barrier height and thus the degradation of subthreshold characteristics is screened out with the modified band diagram shown in Fig. 3-7 (b). Under reverse-mode of measurements the voltages applied to the nominal drain and source of the TT are switched, the band diagram changes to that shown in Fig. 3-7 (c). Under the situation the carriers are still obstructed by the potential energy hump leading to the degradation in the on-current.
Moreover, the subthreshold characteristics of MTs contained in the same test structure studied in Fig. 3-6 are shown in Fig. 3-8. The on-current degradation of DMT is the most obvious, while both SMT and CMT exhibit negligible shift in ID-VG curves. In Figure 3-9, it shows that much severe on-current and subthreshold swing degradation, and threshold voltage shift occur in the short-DMT than the TT and the other MTs do. The reverse-mode measurement of the short-DMT shown in Fig. 3-9 (b) also reveals the effect of potential energy hump property near the drain side. These results unambiguously show that the major
damages are induced in the region of short-DMT and DMT, including the ungated drain region of the TT.
By increasing the absolute magnitude of the drain stress bias, the carriers may obtain more energy to generate more damage near the drain side of the channel due to the increased electric field. Figure 3-10 shows the on-current degradation of TT and different MTs as a function of stress VD with VG= -7.5 V for 1000 sec. The on-current degradation of TT and DMT becomes much severe with increasing magnitude of the drain stress bias. Moreover, in Fig. 3-11, because the vertical electric field near the drain is increased with increasing absolute magnitude of the drain bias, more electrons generated by impact ionization are trapped in the gate oxide near the drain side and result in the positive threshold voltage shift of DMT. These results fit in with our experimental observations. Note that the threshold voltage of TT shows negative shift as the absolute drain bias is high. This is attributed to the severe degradation of subthreshold swing due to the large amount of defects generated in the channel during the stress.
Figure 3-12 shows the on-current degradation of TT and different MTs as a function of stress VG with VD= -25 V for 1000 sec. It can be seen that the trend of on-current degradation of TT and DMT are similar, indicating that the major damage region of the test transistor is located near the drain side. When the absolute gate voltage is lower than the
Figure 3-12 shows the on-current degradation of TT and different MTs as a function of stress VG with VD= -25 V for 1000 sec. It can be seen that the trend of on-current degradation of TT and DMT are similar, indicating that the major damage region of the test transistor is located near the drain side. When the absolute gate voltage is lower than the