HC Stress under Severe Stress Bias

In Fig. 3-6, the test transistor was stressed under a hot-carrier stress biases of VG = -7.5 V and VD = -25 V, much severe than that executed in the previous section, for 1000 sec. As expected, the resultant degradations in the device characteristics in terms of increased subthershold slope and reduced on-current are much bigger than those under mild stress shown in Fig. 3-2. In Figure 3-6(a), relative to the post-stress ID-VG curve which was measured at high absolute drain bias of VD=-3 V, the shift of ID-VG curve after hot-carrier DC stress is more significant when the lateral test transistor was measured at low absolute drain

bias of VD=-0.1 V. This represents an evidence that most of the damage events occur in the channel near the drain side of the test transistor [44]. Hot-carrier stress can generate extra interface states and/or grain-boundary defects, and form a defect-rich and resistive region in the channel near the drain side [45]. As a larger absolute magnitude of drain bias is applied during the measurements of transfer characteristics, the depletion region near the drain side extends more deeply into the channel and effectively screens out the defects induced in the region, thus relieving the post-stress ID–VG shift. In contrast, the subthreshold characteristics of TT under reverse-mode shown in Fig. 3-6(b) show clear shift after stress regardless of the drain bias (-0.1 or -3 V). Under such mode of measurements the damaged region which contributes a high resistance is close to the source side and cannot be screened out by the drain bias. The situation can be schematically illustrated in Figure 3-7 [46].

Damage induced by hot carriers can form a potential energy hump near the nominal drain side of the TT, as shown in Fig. 3-7 (a). A high absolute drain bias tends to drop the energy barrier height and thus the degradation of subthreshold characteristics is screened out with the modified band diagram shown in Fig. 3-7 (b). Under reverse-mode of measurements the voltages applied to the nominal drain and source of the TT are switched, the band diagram changes to that shown in Fig. 3-7 (c). Under the situation the carriers are still obstructed by the potential energy hump leading to the degradation in the on-current.

Moreover, the subthreshold characteristics of MTs contained in the same test structure studied in Fig. 3-6 are shown in Fig. 3-8. The on-current degradation of DMT is the most obvious, while both SMT and CMT exhibit negligible shift in ID-VG curves. In Figure 3-9, it shows that much severe on-current and subthreshold swing degradation, and threshold voltage shift occur in the short-DMT than the TT and the other MTs do. The reverse-mode measurement of the short-DMT shown in Fig. 3-9 (b) also reveals the effect of potential energy hump property near the drain side. These results unambiguously show that the major

damages are induced in the region of short-DMT and DMT, including the ungated drain region of the TT.

By increasing the absolute magnitude of the drain stress bias, the carriers may obtain more energy to generate more damage near the drain side of the channel due to the increased electric field. Figure 3-10 shows the on-current degradation of TT and different MTs as a function of stress VD with VG= -7.5 V for 1000 sec. The on-current degradation of TT and DMT becomes much severe with increasing magnitude of the drain stress bias. Moreover, in Fig. 3-11, because the vertical electric field near the drain is increased with increasing absolute magnitude of the drain bias, more electrons generated by impact ionization are trapped in the gate oxide near the drain side and result in the positive threshold voltage shift of DMT. These results fit in with our experimental observations. Note that the threshold voltage of TT shows negative shift as the absolute drain bias is high. This is attributed to the severe degradation of subthreshold swing due to the large amount of defects generated in the channel during the stress.

Figure 3-12 shows the on-current degradation of TT and different MTs as a function of stress VG with VD= -25 V for 1000 sec. It can be seen that the trend of on-current degradation of TT and DMT are similar, indicating that the major damage region of the test transistor is located near the drain side. When the absolute gate voltage is lower than the threshold voltage, not enough carriers are induced in the channel, so the degradation is not serious. When the absolute gate voltage is larger than threshold voltage and a high absolute drain voltage is applied, it can induce a significant amount of hot carriers and the resultant damage. In Fig. 3-12 the degradation peaks at a gate voltage of -7.5 V. As the absolute gate voltage gets larger, the degradation in on current is decreased. This might be due to the reduction of maximum field strength inside the channel.

The threshold voltage of TT and different MTs as a function of stress VG with VD= -25 V

for 1000 sec is shown in Fig. 3-13. It can assist us to more clearly understand the results shown in Fig. 3-12. We can see that the effect of gate voltage is most significant for DMT.

When the absolute gate voltage is very low and close to VG=0 V, it will induce a very high vertical electric field across the oxide near the drain side and cause a lot of electrons to be injected into and then trapped in the gate oxide. The situation is illustrated in Fig. 3-14.

These results in the positive threshold voltage shift of DMT and generate interface states at channel/oxide interface near drain side, and leads to the on-current degradation of DMT as shown in Fig. 3-12. As the absolute gate voltage is bigger than the threshold voltage and a high vertical electric field is maintained near drain side, the peak of electric field occurs at the space charge region near the drain side which tends to generate hot carriers and resultant damage. When the absolute gate voltage continues to increase, the peak electric field in the space charge region weakens and the high-field region distributes to the region of DMT.

This leads to more electrons being trapped in the gate oxide in the channel region of DMT to cause positive threshold voltage shift of DMT, as shown in Fig. 3-15. However, due to the decrease in the peak electric field, the degradation is also reduced at a higher absolute gate voltage.

To summarize, the MTs contained in the HC-TFTs show the capability of resolving the detailed degradation mechanisms occurring at different parts of the conventional channel.

Moreover a high sensitivity is also demonstrated. Therefore the special design of the HC-TFTs can be employed to help identify the major damage location.

Chapter 4

HC-TFTs under AC stress

In this chapter, the hot-carrier induced degradation in TFTs under dynamic operations is investigated using the proposed HC-TFTs structure. The test samples were prepared with the same method described in previous chapter and detailed process flow can be found in Chapter 2.

4.1 AC Stress Conditions

Figure 4-1(a) shows the waveform of the AC signal applied during stress. The basic parameters of AC signal include frequency (Freq.), signal high level (VG_high), signal low level (VG_low), low-level time (t low), rising time (tr), falling time (tf), and duty ratio.

Under AC stress, a pulse voltage is applied to the gate by Keithiley 4200-PG2 pulse generator, source is grounded and a high absolute voltage (negative for p-channel devices) is applied to the drain, as shown in Fig. 4-1(b). Falling time (tf) is the time that voltage signal falls from 90% to 10% of the amplitude (VG_high – VG_low), while rising time (tr) is defined as the time that the voltage signal rises from 10% to 90% of the amplitude (VG_high – VG_low).

Duty ratio is defined as the ratio of the time when pulse voltage is VG_low (t low in Fig. 4-1(a)) to the duration of one pulse cycle. The total stress time is the summation of tlow under the stress condition. The standard AC stress condition used in the experiment is with gate voltage swing from -10 V (VG_low) to 0 V (VG_high), drain voltage of -25 V, frequency of 500 kHz, both tr and tf of 100 ns, duty ratio of 50%, and the total stressing time (total t low) of 500

sec. Certainly more information could be acquired as the above parameters are varied to study their impact on the device degradation. In this study, the frequency is varied from 100 kHz to 1MHz, and both tr and tf are varied from 100 ns to 10 ns.

4.2 Effects of Frequency

Typical characteristics of the transistors contained in a test sample stressed under the standard AC stress condition with total stress time (total t low) = 500sec are shown in Fig. 4-2 and Fig. 4-3. Fig. 4-2 shows ID-VG curves of the TT before and after AC stress under normal- and reverse-mode of measurements, respectively. With such stress condition, hot-carrier induced degradation is so minor and difficult to detect with the TT. This is similar to the situation encountered in previous chapter and again we can employ the MTs also embedded in the same test structure to help address the issue, and the results are shown in Fig. 4-3. In Figs. 4-3 (a) and (b), it can be seen that the SMT and CMT exhibit negligible degradation in the ID-VG curves after AC stress. In contrast, Figs. 4-3 (c) and (d) show significant shift in subthreshold characteristics of DMT and short-DMT. Device degradations in terms of on-current degradation and threshold voltage shift are observed obviously after AC stress. This is an indication that defects, like interface states and traps in the grain-boundaries are generated and form a defect-rich region. Moreover, electrons are trapped in the gate oxide near the drain side of TT after the AC stress. Again, these effects can be easily detected by the DMT and short-DMT, demonstrating the greater sensitivity of the proposed structure over the conventional test structure. Basically, the features associated with the AC HC stress are similar to those under static stress presented in last chapter.

To more clearly understand the AC effect on the device degradation, frequency of the AC signal was varied. Figure 4-4 shows the subthreshold characteristics of devices stressed before and after 500 sec AC stress with 100 kHz and 1 MHz. In the figures major

parameters of the AC stress are the same as those in standard condition except the frequency.

Fig. 4-5 shows the subthreshold characteristics of the DMT and short-DMT corresponding to the devices studies in Fig. 4-4. In these figures, it can be seen that the degradation of device under high-frequency AC stress is much severe than that under low-frequency AC stress.

Figure 4-6 and Fig. 4-7 show the on-current degradation and threshold voltage shift of TT and MTs after 500 sec AC stress as function of frequency, respectively. The results indicate that the damage induced in SMT and CMT is negligible and almost independent of the frequency.

The on-current degradation is significant for the TT and DMT and increases with increasing frequency. This indicates that additional damage is generated near the drain side as the frequency increases. Moreover, the DMT always shows higher degree of degradation as compared with the TT. This is especially true in detecting the threshold voltage shift, as shown in Fig. 4-7, in which only the DMT shows significant shift. These results clearly demonstrate that the MTs of test structure can definitely resolve the non-uniform damage location and their excellent sensitivity for detecting the frequency-dependent degradation.

Note in the measurements just mentioned, the total time under VG_low is fixed at 500 sec, so the repetitions of the transient stages (tr and tf) are very likely the reason for the additional damage. Therefore, we identify the effect of transient stages under hot-carrier AC stress in the next section.

4.3 Effects of Transient Stages

4.3.1 Rising time

In this section we first investigate the effect of rising time. Parameters of the stress condition are the same as the standard one except the rising time. Fig. 4-8 and Fig. 4-9 show subthreshold characteristics of TT, DMT and short-DMT before and after AC stress with the rising time of 100 ns and 10 ns, respectively. The results show that the device performance

degrades more under a faster rising time of AC stress. Fig. 4-10 and Fig. 4-11 show the on-current degradation and threshold voltage shift, respectively, under AC stress with tf = 100 ns but with varying tr. Still, the DMT exhibits the most serious degradation. Moreover, the damage becomes even more severe as the rising time is shortened.

The degradation mechanism in the transient stage from VG_low to VG_high under AC stress is illustrated in Fig. 4-12 [47]. As shown in the illustration, a high absolute pulse voltage is applied to the gate while the source is grounded and a high absolute bias is applied to the drain. For gate pulse at VG_low of -10V, a sheet of holes is induced in the channel and the damage can be attributed to impact ionization occurring near the drain side, as shown in Fig.

4-12(a), and results in on-current reduction and threshold voltage shift. This is basically the same situation encountered in static HC stress. During the transient period (VG_low rise to VG_high), the inversion holes remained in the channel are mainly attracted by the negative drain bias and accelerated toward the drain, resulting in additional damages and more electrons trapped in the gate oxide, as shown in Fig. 4-12(b). In the case of a slow rising time, most of the holes have enough time to relax through collisions. Thus, the hot-carrier issue is also relaxed. On the other hand, in the case of a fast rising time, the voltage drop across the drain junction is increased by ΔE (Fig. 4-12) in a short time, and more hot holes are expected to be generated, causing more damage in the regions of channel near the drain of the TT. For this reason, the on-current degradation of TT and DMT, and the threshold voltage shift of DMT are relating to rising time during AC stress.

4.3.2 Falling time

Parameters of the AC stress condition are the same as the standard one except the falling time. Figure 4-13 and Fig. 4-14 show ID-VG curves of TT, DMT and short-DMT before and after AC stress with falling time of 100 ns and 10 ns, respectively. The results indicate that

the degradation of device under the AC stress is higher as the falling time becomes shorter.

Figure 4-15 and Fig. 4-16 show the on-current degradation and threshold voltage shift, respectively, under AC stress with fixed tr = 100 ns as function of tf. Comparing the on-current degradation and threshold voltage shift of the three MTs under AC stress, only those of the DMT increase dramatically with decreasing falling time, indicating that additional defect generation and electron trapping in gate oxide occur as the falling time is shortened.

Fig. 4-17 shows a scenario proposed for explaining the effect of falling time under AC stress. When a VG_high = 0 V is applied to the gate, high gate-induced drain leakage by BTBT (Fig. 4-18)dominates the conduction due to the high voltage difference between the gate and the drain, as shown in Fig. 4-17(a). Under the situation, the channel field is more or less uniform, and the electrons appear at the tunneling junction (i.e., drain junction of the TT) would drift toward the source by the field. When the gate voltage is switched from VG_high to VG_low, a high voltage drop is developed at the channel/drain junction in a short time due to the formation of the inversion hole layer, as shown in Fig. 4-17(b). Portions of the electrons remained at the original tunneling junction would be accelerated by the suddenly presenting field. This leads to the generation of hot electrons and the following additional damage, including defect creation in the channel and electron trapping into the oxide (near the drain of the TT). Such phenomenon becomes more significant as the falling time is reduced. This explains why the on-current degradation of TT and DMT shown in Fig. 4-15, and threshold voltage shift of DMT shown in Fig. 4-16.

Chapter 5

Conclusions & Future Work

5.1 Conclusions

In this study, we have employed a novel test structure, the HC-TFT, to investigate the reliability issues of p-channel poly-Si TFTs. This unique test structure is designed for spatially resolving the location-dependent damage induced by hot carriers in either DC (static) or AC (dynamic) stress tests for p-channel poly-Si TFTs.

Whether static or dynamic stress, we can clearly identify that major damage is induced near the drain side of the TT in the test structure by means of the DMT and short-DMT.

Moreover, electron trapping in the gate oxide near the drain side of the TT is also detected by DMT and short-DMT. In addition to the capability of spatially resolving the damage location, the proposed structure also exhibits higher sensitivity.

The HC-TFT was also employed to analyze the effects of several factors including frequency, rising time and falling time, on the damage under AC stress. Our data indicate that the device degradation under high-frequency AC stress is much worse than that under low-frequency. Moreover, the results provide unambiguous evidence that the additional damage occurs during both the voltage falling stage and rising stage. In this thesis physical degradation models have been proposed to explain those findings.

5.2 Future Work

In addition to the hot-carrier degradations in p-channel poly-Si TFTs, negative bias

temperature instability (NBTI) is another key reliability issue that is of immediate concern for practical applications of p-channel poly-Si TFTs. Unfortunately, few efforts are done for investigating the mixed effects of hot-carrier effect and NBTI. This topic is thus important and in the future, and the HC-TFT should be a useful test vehicle for this purpose. It should be also capable of identifying the degradation mechanism in different parts of the channel under various HC/NBTI stress conditions.

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