Chapter 6 Conclusions
6.5 Future Work
We have done and solved, comparatively, some of test power and test data reduction problems, however, there are still problems related with these two issues which deserved further study. In the following, we propose some of topics which could be for future research:
On low power testing:
l Reducing not only the scan-in power, but also scan-out power and capture power.
l Finding scan architecture with reasonable hardware overhead and design effort.
l Reducing the DFT impact as much as possible (such as keeping the performance .of the CUT, considering the physical routing problem).
l Automating the low-power testing DFT synthesis flow.
l Combining low-power testing DFT schemes to the test compression schemes and delay test.
On test data compression:
l Increasing the test compression efficiency.
l Reducing the DFT impact and area overhead.
l Making test compression schemes scaleable to large-scale designs.
l Combining low-power testing DFT schemes to achieve low power test
compression.
l Applying the compression methods also to delay test patterns.
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學經歷
姓 名：林世平 性 別：男
籍 貫：臺灣省台中市
出生日期：民國六十七年二月九日
通訊住址：台中縣大里市長榮里和平街 20 號，電話：(04)24819136 學 經 歷：民國九十二年九月至民國九十六年九月
國立交通大學電子研究所博士班 民國八十九年九月至民國九十一年六月
國立交通大學電子研究所碩士班 民國八十五年九月至民國八十九年六月
國立交通大學電子工程學系
論文題目：低耗能並考慮低成本效益之系統晶片測試策略
Low Power and Low Test Data Volume Testing for Scan Design VLSI
著作目錄 (新法)
(A) International Journal:
[1] (長) S.-P. Lin, C.-L. Lee, J.-E. Chen, J.-J. Chen, K.-L. Luo, and W.-C. Wu, “A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting- in Power for Multiple Scan Design, ” accepted by IEEE Trans. VLSI Systems, 2007
(B) Other Journal Papers:
[1] (長)S.-P. Lin, C.-L. Lee and J.-E. Chen, “Cocktail Random Access Scan for Test Data and Power Reduction, ” Journal of the Chinese Institute of Electrical Engineering, Vol. 13, No. 3, pp. 293— 303, 2006
(C) International Conference:
[1] S.-P. Lin, C.-L. Lee and J.-E. Chen, “A Cocktail Approach on Random Access Scan toward Low Power and High Efficiency Test,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 94--99, 2005.
[2] S.-P. Lin, C.-L. Lee and J.-E. Chen, “A Scan Matrix Design for Low Power Scan-Based Test,” in Proceedings of IEEE Asian Test Symposium (ATS), pp. 224--229, 2005.
[3] S.-P. Lin, C.-L. Lee and J.-E. Chen, “Adaptive Encoding Scheme for Test Volume/Time Reduction in Soc Scan Testing, ” in Proceedings of IEEE Asian Test Symposium (ATS), pp.
324--329, 2005.
[4] S.-P. Lin, C.-L. Lee, J.-E. Chen, J.-J. Chen, K.-L. Luo, and W.-C. Wu, “A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs,” accepted by International Test Conference (ITC), 2006.
(C) Local Conference:
[1] S.-P. Lin, C.-L. Lee and J.-E. Chen, “Scan Matrix: A Low Power Scan Architecture,” in Proceedings of The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.
[2] S.-P. Lin, C.-L. Lee and J.-E. Chen, “Cocktail Scan for Low Power and High Efficiency Test,” in Proceedings of The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug.
2005.
[3] S.-P. Lin, C.-L. Lee and J.-E. Chen, “Adaptive Encoding: A Test Compression Scheme for Soc Testing, ” in Proceedings of The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.