Pattern Fillings for Test Power Consideration

application time (ATE cycles) for a test pattern is



( . When b is large, L becomes smaller; therefore, the time to load a test

pattern in Step 3 is negligible as compared to the shift time of Step 2. Hence, only the shift time needs to be considered. As the test data volume is reduced, the test time is also reduced. Hence the test application time of the Adaptive Encoding scheme is also efficiently short. For the two phase test, for applying random patterns of the first phase, only b bits loading time and L cycles for shift length are needed (the additional header bits shifting is also negligible).

4.7 Pattern Fillings for Test Power Consideration

Test power is also an important problem to be considered during test pattern compression. To reduce the test power, don’t care bits of test patterns are filled with

“0” and “1” to reduce the number of transitions when shifting patterns. However, the strategy to get low power test is somewhat contrary to the strategy to obtain test compression. Some traditional approaches used minimum transition filling (MTF) to reduce test power [8]. However, MTF is not directly applicable for the proposed Adaptive Encoding since it may significantly increase the number of bit flips, consequently, decrease the test compression efficiency. To make a tradeoff between the two strategies, we propose a modified strategy, Constrained MTF, for which only part of unspecified bits of the pattern is to be filled with MTF, to be incorporated with

the encoding scheme.

In developing Constrained MTF, we use the Weighted Transition Count (WTC) [60]

to estimate for power cost. The concept of WTC is to give more costs for bits at the front positions of test patterns since they pass more scan cells and cause more transitions. We give higher priority to apply the MTF strategy to the former bits than to the latter bits of a pattern. To determine which bits are to be applied MTF, a cond ition is used to for judgment :

α×(reduced WTC) ﹣(1 ﹣α) ×(increased bit flips)＞0

where α is a user defined value between 0 and 1. With this condition, the proposed Constrain MTF is : For each scan chain, we start to check each don’t care bit to see whether the above condition is met under a givenα. If the number of reduced WTC of a don’t care bit applied with MTF is larger than the number of increased bit flips, the condition is satisfied and the Constrained MTF is applied. If the condition is not satisfied, MTF is not applied for the bit. This measurement guides us to make a tradeoff between the increased number of bit flips and the amount of reduced WTC when a bit is to be filled with MTF. If we want lower test power, we should choose a larger α so that more bits satisfy the condition. However, this means that compared with the original achievable test compression with Adaptive Encoding, more number of bit flips are added. If we choose α to be smaller, fewer don’t care bits are filled with MTF. For this case, we obtain little test power gain. We note that when we make α be 1, the proposed MTF becomes the traditional MTF; and whenα be 0, it equals to the Adaptive Encoding scheme without any MTF strategy.

In Figure 4.10, an example is shown with a test pattern applied with Constrained MTF along with no filling and the traditional MTF strategy respectively. For the Constrained MTF, the number of flips is 9, only one more than that of the no-filling

case. Its WTC is 29, which is much less than that of the without-filling case but only a moderate increase as compared to that of the traditional MTF case.

Adaptive Encoding, no filling (α= 0) Resulted pattern in memory # Flips #WTC xx10xxxx111xx1x1 + 0000000000000000 = 0010000011100101 6 82 Vector with Constrained MTF (α= 0.05)

xx10xxxx11111111 + 0000000000000000 = 0010000011111111 9 29 Vector with traditional MTF (α= 1)

1110111111111111 + 0000000000000000 = 1110111111111111 15 7 lower power higher

compression

Figure 4.10 An example pattern with three different filling strategies which result in different number of flips and WTC's

4.8 Experimental Results

This Adaptive Encoding scheme had been implemented in C++ and applied to some largest ISCAS89/ITC99 scan circuits and locally designed circuits, which had even higher complexity. The test patterns for the circuits were obtained by SYNTEST tools. The results obtained are then compared with those obtained by applying some other methods [47, 51, 53-55] as shown in Table 4.1, where m is the optimal group size for Golomb [53] or the optimal block size for BR [51]. As for Selective Huffman [54], we choose the block size as 12 bits and the number of encoded states is 16. In the table, for the VIHC method, the compression/reduction is listed for the group size of 16 and for the unlimited group size respectively. The column “Max Red.” is its theoretical encoding upper bound that is practically not realizable. It should be mentioned that for the Entropy-related methods, larger group size implies larger area of the decoder and larger synchronization overhead between the decoder and the ATE.

In the table, it can be seen that our proposed method outperforms the Correlation-related methods, RAS and BR, for all the circuits, and furthermore, it can

get compression ratios, which are comparable to the theoretical compression upper bounds of the VIHC method, especially for the larger size circuits: leon1, leon2, rca and fft. Also, Adaptive Encoding is very efficient for test compression especially in very large-scale designs.

Table 4.1 Compression comparison between different encoding methods

Entropy-Related Methods Correlation-Related Methods VIHC [55]

Golomb [53] BR [51]

Circuit Patterns SFFs

m Red.

Table 4.2 compiles the test speedups of the Adaptive Encoding method and the BR method as compared with the traditional serial scan design. Test time is calculated based on the analysis in Section 4.6. In the table, the memory size for patterns for each circuit is listed and m is the number of scan chains and r is the speed ratio between the system clock and the test clock as is defined in Section 4.6. The column

“Area Over. ” is the area overhead for the decoder machine, which was synthesized by Synopsys Design Compiler, and memory is not counted. For the Adaptive Encoding method, the ATE repeats filling scan data during the period when the decoder machine is shifting a pattern into scan chains. Therefore, compared to BR, it needs additional loading time overhead as analyzed in Section 4.6. Even so, the Adaptive Encoding method still obtained higher speedups. The speedups obtained for the Adaptive Encoding method is 16.46 for r = 5 (the bold character cases) with only a little area

overhead of the decoder.

Table 4.2 Test speedups for BR and Adaptive Encoding under different number of scan chains, m, and clock ratio, r, between test clock and system

clock

Adaptive Encoding

m = 16 m = 256 m = 1024

Circuit BR RAM

r = 2 r = 5 r = 10 Area

Over. % r = 2 r = 5 r = 10 Area

Over. % r = 2 r = 5 r = 10 Area Over. %

s35932 1.50 2K 1.78 1.84 1.87 4.0 - - - - - - - -

s38417 1.22 2K 1.66 1.72 1.73 4.4 - - - - - - - -

s38584 1.52 2K 2.07 2.15 2.18 4.9 - - - - - - - -

b18_1 2.74 4K 3.55 3.81 3.90 1.0 - - - - - - - -

b19_1 1.95 8K 3.65 3.92 4.01 0.5 4.09 4.11 4.11 1.9 - - - -

b22_1 1.76 1K 2.32 2.42 2.46 3.8 - - - - - - - -

leon1 8.41 16K 8.24 9.74 10.37 0.7 10.85 10.99 11.04 2.7 11.03 11.06 11.08 9.1 leon2 40.98 64K 20.23 32.59 40.93 0.1 49.69 52.76 53.85 0.5 53.56 54.45 54.75 1.8 rca 46.29 32K 20.92 34.43 43.87 0.3 54.07 57.73 59.06 1.3 58.72 59.75 60.10 4.4 fft 16.26 128K 14.22 19.39 22.06 0.1 24.38 25.09 25.34 0.4 25.28 25.47 25.53 1.4

Avg. 12.26 16.46

Table 4.3 shows the experimental results on the tradeoff between test compression and test power reduction for incorporating the Constrained MTF strategy with the encoding scheme. In the table, number of chains, WTC and peak transitions, and data reduction ratio for each circuit are listed for results of our Adaptive Encoding without and with the Constrained MTF of different values of α’s. We can see that when circuits have higher complexity, a larger α, for example, 0.1 should be chosen. Take the circuit “leon1 ” to be an example, with α = 0.1, we reduce the test energy by (57.8M-4.85M)/57.8M = 91.60% and reduce the peak power by (5156-4353)/5156 = 15.57% at the expense of 10.82% loss in test compression. Another circuit example:

“rca” with α = 0.1, we reduce the test energy by (1.17G-57.2M)/1.17G = 95.11%

and reduce the peak power by (10467-9415)/10467 = 10.05% at the expense of only 4.31% loss in test compression. The larger the circuit is, the more power saving can

be achieved with a little loss of test compression. When we make α = 1, i.e., traditional MTF is used, we almost can not obtain any compression since too many bit flips are introduced.

Table 4.3 Tradeoff between test power and test compression for different user defined values

Adaptive Encoding with constrained MTF Without

Finding a suitable α not only reduces test power significantly but also obtains satisfactory test compression. We did an experiment on the circuit “b19_1” with different α’s ranging from 0.01 to 1 and plot the results of test compression, test energy and peak power with respect to the value s of α’s in Figure 4.11. From the figure, we observe that for this case, the most suitable α for “b19_1” is 0.15, for which a 45.22% test compression, a 83.63% test energy reduction and a 32.25% peak power reduction is obtained by Adaptive Encoding respectively.

0

Figure 4.11 Experimental results on test data compression, test energy and peak power (transitions) for different value of α on circuit b19_1. The most suitable value for α is 0.15 to obtain a 45.22% test compression, a 83.63%

energy reduc tion and a 32.25% peak power reduction.

Table 4.4 shows the results of the experiments on incorporating the two phase test generation technique and the test vector reordering technique in the Adaptive Encoding scheme. In the table, the second column lists the test data volume for the Adaptive Encoding without incorporating the two techniques, the third column lists the test data volume of the Adaptive Encoding applied with the test vector reordering (TVO) technique, and the fourth column lists the test data volume of using the two phase test generation technique to generate test patterns, which gave the same fault coverage as that of the test sets of the second column, and the patterns were then applied with the TVO again to reduce their volume. For the last column, the data volumes for the random phase and the deterministic phase respectively of the two phase test generation technique are also included. For the test data volumes in second and third columns, since the test patterns were obtained for circuits from a

commercial tool SYNTEST and were very compact, applying the TVO technique obtained some reduction although the reduction was not significant. However, for the test data volume in the fourth column, the final test data volume obtained by applying the two-phase test with TVO is greatly reduced. This shows that applying the Adaptive Encoding in conjunction with the two phase test generation and the TVO techniques can greatly reduce the test data volume.

Table 4.4 Data volume for Adaptive Encoding with different techniques

Circuit Adaptive

Encoding TVO Two-Phase & TVO (first phase + second phase) s35932 32864 31132 9380 (680 + 8700) s38417 120893 117219 60890 (800 + 60090) s38584 91630 85453 53635 (2550 + 51085)

b18_1 368226 352604 247195 (14080 + 233115) b19_1 767955 743934 518219 (17700 + 500519) leon1 561574 494816 335176 (22400 + 312776)

4.9 Summary

In this work, we have proposed an Adaptive Encoding scheme to encode the test data (patterns) to save the test data volume and the test application time. The scheme handles, instead of the data themselves, the difference between two consecutive test patterns by using packets, making the test data be encoded in variable sizes to achieve better data compression. A decoder machine is proposed to make the scheme possible and to decode the encoded data. Constrained MTF, a filling strategy, is also proposed to be adopted with the scheme to simultaneously achieve test compression and test power reduction. In addition, the scheme can incorporate the techniques to generate test patterns in two phases and to reorder the test vectors to further achieve the test data reduction. Experimental results have shown that the proposed encoding scheme

is very effective in reducing the volume of test data and test power, and in speeding up test application time for large-scale designs.

Chapter 5 Low Power Test Compression for