Hardware Modifications

In order to facilitate the proposed clock scan based on RAS scheme, some hardware modifications need to be done:

3.3.3.1 Modified Address Register

Since the RAS architecture does not support serial scan, scanning in seed patterns is costly. It will take m*(address width+1) clock cycles to scan in an m-bit seed pattern.

In order to facilitate the SRST, the address shift registers (ASRs) of the RAS circuit need to be modified as shown in Figure 3.7. The modified ASRs has two modes, i.e., when Mode = 1, which is the SRST mode, ASRs act as a counter; when Mode = 0, which is the conventional RAS mode, ASRs act as a shift register. With this modified ASRs, an m-bit seed pattern needs only m clock cycles to be scanned in.

Si Mode

D Q

Q Reg

Q Reg

Q Reg

D Q D Q

Figure 3.7 The proposed address shift register (3 bits)

3.3.3.2 On-Chip Scan Controller

An on-chip scan controller is also needed to switch between the SRST mode and the RAS mode. The controller mainly contains several counters to monitor the number of scan- in bits, test length applied and number of scan- in seed patterns. The controller also controls ACLK and SCLK to correctly scan or capture test responses.

The proposed test flow shows in Figure 3.8.

1. SRST Mode

1.a Load a seed from ATE.

1.b Perform CFST with L test cycles . 1.c If another seed exists, go to 1.a.

2. RAS Mode

2.a Load bit-flip data from ATE until a test cube is completely loaded.

2.b Perform test.

2.c If another test cube exists, go to 2.a.

Figure 3.8 The proposed Cocktail Scan flow

3.4 Experimental Results

Experiments had been done to verify the proposed scheme. Two experiments’ data are given:

3.4.1 Experiment on Test Efficiency of the Proposed Process Compared with Other Processes

First, Table 3.3 shows the experimental results of applying the CSC and BPBTVD strategies in the test vector and bit flipping reduction process to a benchmark circuit s5378. The results are compared with those applying the traditional process of first applying SC, LKH (Lin-Kernighan Heuristic) reordering, and then TVD [48]. The original number of test vectors was 1126 with fault coverage of 99.12%. After the

traditional process was applied, 272 vectors were obtained but the number of bit flipping was 4720. For our proposed process applied, 640 vectors was obtained first after CSC but a far less number of bit flipping, 1173, was obtained after BPBTVD. In the RAS architecture, the number of bit flipping is the most important factor since it determines the test data volume, test time and test power. Also, it is noticed that for the traditional process, after SC, the bit flips increased significantly and LKH only improved 6% of bit flips, but for our proposed process, LKH reduced bit flips significantly and CSC did not increase bit flips which were further reduced by BPBTVD. For our proposed process, the results of TVD are also listed. Although reducing more bit flips, it suffered a slight decrease on the fault coverage.

A more comprehensive experiment on larger benchmark circuits for test efficiency of the proposed process compared with other processes is shown below. Table 3.4 lists the benchmark circuits on which the experiment was performed with their associated information, where circuit name, number of inputs/outputs, number of gates, number of test patterns, which includes number of fully-specified (FS) test patterns (i.e., no don’t care bits) and number of partially specified (PS) test vectors (i.e., with don’t care bits), number of scan cells, and test efficiency are included respectively.

Table 3.5 lists the experimental results of applying the traditional process [48], a RAS process which is similar as that of [47] and our proposed process on the partially specified test vectors of above circuits. For the RAS process experiment, test responses were stored back to SFFs to be compacted with input vectors, while for the proposed process experiment, test responses were abandoned. The skills such as Hamming Distance Reduction, etc., were not implemented in both the RAS experiment and the proposed process experiment since we only wanted to compare the result of the strategy of Test Response Abandonment with that of the general practice of compacting input vectors with the output responses. In the table, the final

reduced number of test vectors, the number of bit flips, the data volume for storing test vectors, and test application cycles are listed. For the traditional process experiment, Optimistic cost model was used similar to that used in [48]. The results show that our proposed process is a great improvement on the number of bit flips and consequently on the data storage volume (in average, by 65.07% reduction over those of [48] and by 74.30% over those of [47]) and test application time (in average, by 2.96 times reduction over those of [48] and 4.56 times reduction over those of [47]), for all circuits. In the above experiments, ATALANTA [32] was used as the test generator for generating the test patterns. Since ATALANTA cannot produce complete PS test vectors for larger circuits, we only applied the obtained PS test vectors to the last five circuits in Table 3.5.

Table 3.3 Comparison of traditional process and the proposed process on CSC and BPBTVD strategies on s5378

Traditional [48] Proposed

s5378

Original SC LKH TVD Original LKH CSC TVD BPBTVD

Vectors 1126 305 305 272 1126 1126 845 640 640

Flips 3505 5286 4972 4720 3505 1213 1213 1124 1173

FC 99.12 99.12 99.12 99.12 99.12 99.12 99.12 99.10 99.12