Chapter 1 Introduction
1.5 Gate Engineering
For the consideration of low power consumption, high speed and high packing density in system on a panel, there is a need to scale down poly-Si TFTs’ device geometries However, scaling down the channel length will leads to undesirable short-channel effects. It will result in the threshold voltage roll-off, degradation in drain breakdown and severe kink effect.
Comparing with single-crystalline Si MOSFET, poly-Si TFTs show more seriously short channel effect due to the presence of rich defect in the grain boundaries which enhance the
improving the quality of poly-Si thin film. The other method is to enhance gate controllability to suppress the large filed near drain by modifying the device structures. Recently, for single-crystalline-Si MOSFETs, lots of efforts on non-planar device structures have been developed for better gate electrostatic control of the channel potential, such as double-gated, triple-gated, Π-gated, Ω-gated, nanowire channel, and GAA [1.54]-[1.58]. Among those, GAA FETs together with the nanowire channel have been reported to be the best structure for extreme geometry scaling [1.56]-[1.58].
1.6 System on a Panel (SOP) Issues
The advantages of integrating poly-Si TFTs circuits in the panel are not only it can allow pixel pitch to go beyond the bonding pitch of IC chips, but also permit to integrate a variety of circuitry not merely drivers [1.59]. However, the poly-Si TFT LCD module still costs a lot and consumes much power since it needs high driving speed and a wide voltage range analog interface [1.60]. If the TFT driver achieves full digital interface of transistor to transistor logic (TTL) or a lower voltage level, the cost of LCD module will be reduced and power consumption will be decreased.
1.6.1 Concept of System on a Panel
In short, the meaning of system on panel can be defined as the entire system integration on a single substrate including active matrix displays, integrated peripheral circuits, memory circuits, and controller circuits [1.60]-[1.63]. The first system on panel prototype was
proposed by Sharp Corp. and Semiconductor Energy Laboratory Co. in 2004, which realizes the integration of CPU, an audio circuit, a graphic controller, and memories on the liquid crystal display by continuous grain silicon (CGS) technology. CG silicon fabricated in low temperature by catalyst assists solid phase crystallization, which doesn’t subject to the effects of variations in laser density [1.64]. This crystallization method offers superior reliability and uniformity. The 8-bit CPU contains about thirteen thousand TFTs and operates at 3MHz with 5V voltage supply.
Various kinds of voltage or signal losses come into existence in the module because the system has to transfer enormous data between the large scale circuits at high frequency [1.60].
If the large scale circuits can be entirely integrated in the same substrate without sacrificing functional properties, the total performance will be improved and the power consumption will be diminished theoretically. More importantly, the size, weight, and cost of the system will be cut down which is beneficial to the consumers.
There are two main considerations to achieve the goal of system on panel. First, the properties of poly-Si TFTs must be improved such as better mobility (larger than 400 cm2/Vs), shorter channel device (less than 1 μm), lower sub-threshold swing (~0.1 V/dec), lower threshold voltage(~±0.7 V), higher on/off current ratio (~109) are needed. Second, the circuit interconnection technique needs to be promoted. When shrinking the transistor size, excellent uniformity and reliability are critically required for the development of SOP.
1.7 Motivation
displays, such as active matrix liquid crystal displays (AMLCDs) [1.1]-[1.7] and active matrix organic light emitting displays (AMOLEDs) [1.8]-[1.14], and potential for 3-dimension ICs’
applications [1.65]. The ability of fabricating high-performance LTPS TFTs enables their use in further applications of SOPs. Therefore, there is great interest in improving the performance of LTPS TFTs. Considering the issues of system on panel (SOP) mentioned in former section, both the LTPS TFT performance and the added-value functionality need to be further promoted and developed. For the further development, high versatile circuits and systems need to be fully integrated to achieve system-on-panel (SOP). As performance and complexity requirements increase, there is a need to scale down device geometries to achieve higher speeds and packing densities. Unfortunately, those undesirable effects in the electrical characteristics that mentioned above become particularly important as the channel length and gate insulator thickness are reduced. Those all are increased with the higher drain electric field near the drain junction. These undesirable effects prohibit the use of poly-Si TFTs in many high-performance circuit applications. Therefore, the drain-field-relief structure plays an essential role for the future prospection. However, those structures often required complicated process (such as, spacer and damascene processes), or additional mask step which may raise the mis-alignment problem. In chapter 2, a novel and simple process was introduced to fabricate T-shaped gate (T-Gate) structures.
Especially for high-speed and low-power applications, the scaled-down LTPS TFTs with high performance are required. Unfortunately, several short-channel effects are known to aggravate with reducing device dimension, such as threshold voltage roll-off, higher subthreshold swing, larger drain-induced barrier lowering (DIBL), and acuter kink effect. The short-channel effects seriously restrict these applications. Recently, for single-crystalline MOSFETs, lots of efforts on non-planar device structures have been developed for better gate electrostatic control of the channel potential, such as double-gated, triple-gated, Π-gated, Ω-gated, NW fin-channel, and gate-all-around (GAA). Among those structures, the GAA
structure with nanowire channels is proposed to be the best structure to provide the immunity of short-channel effects. Additionally, the poly-Si TFTs suffer more serious short-channel effects than SOI devices due to the presence of grain boundary and intra-grain defects in channel region. However, there are few works presented such structures on poly-Si TFTs so far. In chapter 3, the gate-all-around poly-Si TFTs with multiple nanowire channels, for the first time, are proposed by using simple process sequence to achieve high electrical performance and effectively suppress the short-channels effects.
Since the quality of poly-Si active layer places a profound influence on the performance of poly-Si TFTs, crystallization of a-Si thin films becomes the most important process issue in the fabrication of high-performance LTPS TFTs. A good-quality poly-Si thin film always results in good electrical characteristics of poly-Si. Various crystallization technologies have been propose to create high-quality poly-Si thin films on foreign substrates at low temperature, however, most of them are still complex and not easy to control. As a result, in chapter 4, two types of simple process sequences were demonstrated for fabricating gate-all-around LTPS TFTs with high-crystallinity Si nanowire (NW) channels. The one is the excimer-laser-crystallized (ELC) nanowire TFT, in which the nanowire structure features only-one grain boundary. The other is the spacer-patterned nanowire TFT based on large-grain poly-Si thin film prepared with sequential-lateral-solidification (SLS) crystallization, in which the nanowire can be controlled to be approximated single-crystalline.
In addition to promoting the device performance of basic LTPS TFTs, for system-on-panel (SOP) developments, other added-value functional elements based on poly-Si TFT technology, such as memory and display elements are also needed to develop to fully integrate on the same display panel. In chapter 5, we utilized the spacer technique to
1.8 Thesis Organization
In this thesis, various structures and techniques are studied for the fabrication of high-performance low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) through drain, gate, and channel engineering. In addition, for diversified SOP application, the SONOS memory, field emitters and flexible electronics are developed. The outline of thesis organization is shown in Fig. 1-2.
In chapter 2, a novel and simple process was introduced to fabricate T-shaped gate (T-Gate) structures.
In chapter 3, the gate-all-around poly-Si TFTs with multiple nanowire channels are proposed by using simple process sequence to achieve high electrical performance and effectively suppress the short-channels effects.
In chapter 4, two types of novel and simple processes were demonstrated for fabricating high-crystallinely Si nanowire LTPS TFTs with gate-all-around structures for channel engineering development.
In chapter 5, based on previous proposed gate-all-around structure, two kinds of trapping-charge memory devices with field-enhanced nanowire and/or silicon-oxide-vacuum-oxide-silicon (SONVAS) structures were proposed for the first time to improve the memory performance and reliability with a simple process sequence for SOP applications.
In chapter 6, we further applied this technique on two types of field emitters for the opportunity of replacement of LCD display elements in terms of system integration and image performance.
Finally, summary and conclusions as well as recommendation for further research are given in chapter 7 and chapter 8, respectively.
Figures
Fig. 1-1 Development of system on panel (SOP)
Fig. 1-2 Outline of thesis organization.
Chapter 2
Novel T-Shaped-Gate Polycrystalline Silicon Thin Film Transistors with in-situ Embed Vacuum
2.1 Introduction
Poly-Si thin film transistors (TFTs) have been widely applied as switching elements in active matrix liquid crystal displays (AMLCDs),and active matrix organic light emitting diodes (AMOLEDs) [2.1]-[2.5].Unlike the conventional amorphous silicon TFTs, poly-Si TFTs exhibit higher driving current. For further SOP development, high versatile circuits and systems need to be fully integrated on the display panel substrate [2.6], [2.7]. Unfortunately, conventional poly-Si TFTs suffer from anomalous off-state leakage current, serious kink effect, and hot-carrier instability, which are all related to the high electric field near the drain junction. Those undesirable effects prohibit the use of poly-Si TFTs in many high-performance and low-standby-power circuit applications. The dominant off-state leakage current is due to the field emission via grain boundary traps induced by the high electric field in the drain depletion region [2.8], [2.9]. It has been widely reported that the offset-gated and lightly doped drain (LDD) poly-Si TFTs can effectively reduce the maximum drain electric field in the channel. However, the offset-gated poly-Si TFTs cause a high parasitic resistance in the offset region which severely decreases the on-current [2.10], [2.11]. Besides, in LDD
sub-gate structures together with thicker dielectrics below sub-gate, which have lower off-state leakage current, while maintain high turn-on characteristics, as well as free from LDD implant damage, have been reported [2.13]-[2.15]. However, those structures often required complicated process (such as spacer and damascene processes), or additional mask step which may raise the mis-alignment problem [2.16].
In this chapter, a T-shaped-gated (T-Gate) poly-Si thin-film transistor with self-aligned sub-gates and in-situ embed vacuum is proposed and fabricated only with a simple selective side-etching process and without any additional photo-lithography step. Besides, novel vacuum (the lowest permittivity of k=1 in nature) gaps embedded in this T-Gate structure are
in-situ created via capping the SiH
4-based passivation oxide in plasma enhanced chemical vapor deposition (PECVD) system [2.17].The schematic figure of the proposed T-Gate TFTs and its equivalent structure were shown in Figs. 2-1(a) and (b), respectively. The vacuum gaps can reduce the vertical electric field near the drain due to its lowest permittivity of k=1. The vacuum gaps serve as an equivalent thicker oxide. Due to the relative static permittivity SiO2 of 3.9, the equivalent oxide thickness of the vacuum gap is as high as 3.9 times [2.18]-[2.20]. The poly-Si region under vacuum gaps can be considered as the offset region and the gate edge over the vacuum cavity serves as a field plate connected with the main gate, so that the proposed TFT operates similar as the field induced drain (FID) TFTs.
2.2 Electrical Simulations for T-Gate LTPS TFTs with Vacuum Gaps
Device simulation is first carried out to compare the electric field distributions of T-Gate
TFTs with different vacuum-gap thickness (Tvac) and length (Lvac) which are followed by the experimental details of device fabrication. The 2-D numerical simulation was carried out using ISE which is a commonly used numerical simulator for device analysis [2.21].Figs. 2-2 (a) and (b) display the simulated potential contours of the proposed T-Gate and the conventional poly-Si TFTs at VGS = 1.5 V and VDS = 20 V, respectively. It can be seen evidently that in the T-Gate LTPS TFT, the electrostatic potential contours at channel surface near the drain can be relaxed remarkably by the additional offset region and vacuum gap, as compared with that in the conventional device. Under higher negative gate bias, the effective thicker gate insulator resulting from the extra vacuum gap can make less gate voltage couple to the drain junction [2.22]-[2.24].Thus, not only the maximum lateral electric field (EML) but also the maximum vertical electric field (EMV) can be effectively reduced for the proposed T-Gate poly-Si TFT.
Figs. 2-2 (a) and (b) show the 2-D electrical potential distribution of the conventional and T-Gate TFTs, respectively. The dense equi-potential lines near the drain region in conventional TFTs can be significantly relaxed in the T-Gate TFTs, indicating that electric field is consequently reduced by T-Gate structure. Figs. 2-3 (a) and (b) shows the corresponding simulated lateral and vertical electric field distributions along the channel surface near the drain junction for T-Gate TFTs with various Tvac and Lvac, respectively. The maximum lateral and vertical electric field decreases with increasing Tvac and Lvac in the T-Gate TFT. The reduction of vertical electric field is dominated by the vacuum-gap height (Tvac), while reduction of lateral electric field is dominated by the offset length (i.e. the side-etching length, Lvac).
Thus, the maximum electric field near the drain can be effectively decreased by applying
2.3 Experiments
2.3.1 Fabrication Sequence of T-Gate Poly-Si TFTs with Vacuum Gaps
The detailed process flow of device fabrication is shown in Figs. 2-4 (a)-(k). At first, a buffer layer that composed of 50nm-thick SiN and 130nm-thick SiO2 thin films was deposited by plasma-enhanced chemical vapor deposition (PECVD) system on the glass substrate. Then, a 50 nm amorphous silicon (a-Si) thin film was deposited by PECVD system on buffer layer.
Before excimer laser crystallization, dehydrogenation at 500 °C for 15 minutes was carried out to prevent the hydrogen explosion during laser irradiation. The a-Si thin film was transferred into poly-Si by 308-nm XeCl excimer laser with laser energy density of 257 mJ/cm2 and shot overlapping of 99%. After defining the active layer, a 40 nm or 80 nm-thick SiO2 was deposited as gate insulator by PECVD system at 420 °C. A 50 or 100 nm-thick indium tin oxides (ITO) and a 200 nm-thick Mo films were deposited by sputter system at room temperature sequentially. The stacked Mo/ITO films were simultaneously etched to pattern as the gate electrode. An oxalic acid, (COOH)2‧2H2O, solution was then used to selectively etch the ITO layer without harming Mo layer to form the T-shaped structure.
Different side etching lengths of ITO thin film were carefully controlled to 250 and 500 nm confirmed by the scanning electron microscope (SEM) analyses. A self-aligned phosphorous implantation was carried out to form source and drain regions with the implantation energy and dosage of 15 keV and 2 × 1014 cm-2, respectively. Then, a 500-nm-thick inter-layer dielectric of silane (SiH4)-based SiO2 was deposited by PECVD system. It should be noted that the vacuum gaps were in-situ formed during the inter-layer dielectric deposition by PECVD due to the active chemical properties of silane-based (SiH4) free radicals [2.25]. Then, the dopants were activated through rapid thermal annealing (RTA) at 620 °C for 30 seconds.
After standard contact hole opening, 500-nm-thick Al was deposited and patterned as interconnect metal. Finally, some TFTs were subjected to the NH3 plasma treatment at 300 °C for 1 hour to passivate the dangling bonds at the poly-Si/SiO2 interface and the trap-states within the poly-Si film. For the purpose of comparison, the conventional poly-Si TFTs without side-etching process shown in Fig. 2-11(l) were also fabricated with the same process sequence. For all T-Gate devices, the channel length (L) is defined as the length of the patterned Mo gate electrode, the height of vacuum gap (labeled as Tvac) is determined by the thickness of deposited ITO, and the length of vacuum gap (labeled as Lvac) is determined by the length of side-etched ITO. The split conditions of various Tvac and Lvac were designed and listed in Table 2-1. The corresponding SEM images of the fabricated T-Gate and the conventional TFTs are shown in Figs. 2-5 and 2-6, respectively.
2.4 Results and Discussion
2.4.1 Method of Electrical Parameter Extraction
In the whole thesis, all the electrical characteristics of LTPS TFTs were measured by HP 4156C semiconductor parameter analyzer. Extraction methods of all the electrical parameters mentioned in this thesis, including the threshold voltage (Vth), subthreshold swing (S.S.), maximum on-current (Ion), minimum off-current (Ioff) and the on/off current ratio, are introduced.
method, that is, defined as the gate voltage required to achieve a normalized drain current of ID = (W/L)×10-8 A at |VDS| =0.1V.
Field effect mobility (μ)
The field effect mobility is extracted from the maximum transconductance in the linear region of IDS-VGS characteristics at |VDS| = 0.1V using the formula:
, where Cox is the gate oxide capacitance per unit area, and the transconductance (gm) is defined as:
Field effect mobility is an important parameter for carrier transport; it describes how strong the motion of an electron or hole is influenced by the applied electric field.
Subthreshold swing (S.S.)
Substhreshold swing (SS) is defined as:
V
It is a typical parameter to describe the control ability of gate toward channel.
Maximum on-current and Maximum leakage-current
In this chapter, on-current is defined as the drain current measured at VGS= 15V, VDS= 3V. Maximum leakage current is defined as the drain current measured at VGS = -15V, VDS = 3V.
On/off current ratio
The on/off current ratio is defined as the ratio of maximum drain current over minimum drain current at |VDS| = 3 V.
A high performance poly-Si TFT should not only provides high on-state driving current but low off-state leakage current. High on-state driving current means the pixel capacitances could be charged more efficiently during a line access time. Sufficiently low off-state leakage current represents the charged capacitance could remain stable during the much longer frame time. Therefore, on/off current ratio is obviously a more appropriate evaluation parameter compared with on-state or off-state current alone.
2.4.2 Electrical Characteristics of T-Gate TFTs with Vacuum Gaps
Fig. 2-7 shows the transfer characteristics of T-Gate LTPS TFTs with different Tvac and fixed Lvac; while Fig. 2-8 shows those with different Lvac and fixed Tvac. All T-Gate LTPS TFTs are with channel length of 5 μm and channel width of 10 μm, and gate oxide thickness of 400 Å. It is shown that the leakage current of T-Gate LTPS TFTs could be remarkably suppressed without degrading on current significantly. It is attributed to the drain field relief via the offset region and vacuum gap to reduce the leakage current at the off state, and the low series resistance via field plate assistance to maintain the on current at the on state. The leakage current of T-Gate LTPS TFTs could also be further reduced by increasing the Tvac or Lvac due to the more vertical or lateral drain-field reduction, respectively, which is consistent with previous simulated results. For the T-Gate TFTs with Tvac = 100 nm and Lvac = 500 nm,
current ratio could be promoted to beyond 109. Table 2-2 lists the typical electrical characteristics of these devices.
In order to verify the symmetry of self-aligned ITO side etching process, the forward-mode and reverse-mode measurement were carried out, whose corresponding measurement is illustrated in Fig. 2-9. Fig. 2-10 shows the transfer characteristics of the fabricated T-Gate LTPS TFT under forward and reverse modes. There is almost no difference
In order to verify the symmetry of self-aligned ITO side etching process, the forward-mode and reverse-mode measurement were carried out, whose corresponding measurement is illustrated in Fig. 2-9. Fig. 2-10 shows the transfer characteristics of the fabricated T-Gate LTPS TFT under forward and reverse modes. There is almost no difference