Chapter 1 Introduction
1.8 Thesis Organization
In this thesis, various structures and techniques are studied for the fabrication of high-performance low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) through drain, gate, and channel engineering. In addition, for diversified SOP application, the SONOS memory, field emitters and flexible electronics are developed. The outline of thesis organization is shown in Fig. 1-2.
In chapter 2, a novel and simple process was introduced to fabricate T-shaped gate (T-Gate) structures.
In chapter 3, the gate-all-around poly-Si TFTs with multiple nanowire channels are proposed by using simple process sequence to achieve high electrical performance and effectively suppress the short-channels effects.
In chapter 4, two types of novel and simple processes were demonstrated for fabricating high-crystallinely Si nanowire LTPS TFTs with gate-all-around structures for channel engineering development.
In chapter 5, based on previous proposed gate-all-around structure, two kinds of trapping-charge memory devices with field-enhanced nanowire and/or silicon-oxide-vacuum-oxide-silicon (SONVAS) structures were proposed for the first time to improve the memory performance and reliability with a simple process sequence for SOP applications.
In chapter 6, we further applied this technique on two types of field emitters for the opportunity of replacement of LCD display elements in terms of system integration and image performance.
Finally, summary and conclusions as well as recommendation for further research are given in chapter 7 and chapter 8, respectively.
Figures
Fig. 1-1 Development of system on panel (SOP)
Fig. 1-2 Outline of thesis organization.
Chapter 2
Novel T-Shaped-Gate Polycrystalline Silicon Thin Film Transistors with in-situ Embed Vacuum
2.1 Introduction
Poly-Si thin film transistors (TFTs) have been widely applied as switching elements in active matrix liquid crystal displays (AMLCDs),and active matrix organic light emitting diodes (AMOLEDs) [2.1]-[2.5].Unlike the conventional amorphous silicon TFTs, poly-Si TFTs exhibit higher driving current. For further SOP development, high versatile circuits and systems need to be fully integrated on the display panel substrate [2.6], [2.7]. Unfortunately, conventional poly-Si TFTs suffer from anomalous off-state leakage current, serious kink effect, and hot-carrier instability, which are all related to the high electric field near the drain junction. Those undesirable effects prohibit the use of poly-Si TFTs in many high-performance and low-standby-power circuit applications. The dominant off-state leakage current is due to the field emission via grain boundary traps induced by the high electric field in the drain depletion region [2.8], [2.9]. It has been widely reported that the offset-gated and lightly doped drain (LDD) poly-Si TFTs can effectively reduce the maximum drain electric field in the channel. However, the offset-gated poly-Si TFTs cause a high parasitic resistance in the offset region which severely decreases the on-current [2.10], [2.11]. Besides, in LDD
sub-gate structures together with thicker dielectrics below sub-gate, which have lower off-state leakage current, while maintain high turn-on characteristics, as well as free from LDD implant damage, have been reported [2.13]-[2.15]. However, those structures often required complicated process (such as spacer and damascene processes), or additional mask step which may raise the mis-alignment problem [2.16].
In this chapter, a T-shaped-gated (T-Gate) poly-Si thin-film transistor with self-aligned sub-gates and in-situ embed vacuum is proposed and fabricated only with a simple selective side-etching process and without any additional photo-lithography step. Besides, novel vacuum (the lowest permittivity of k=1 in nature) gaps embedded in this T-Gate structure are
in-situ created via capping the SiH
4-based passivation oxide in plasma enhanced chemical vapor deposition (PECVD) system [2.17].The schematic figure of the proposed T-Gate TFTs and its equivalent structure were shown in Figs. 2-1(a) and (b), respectively. The vacuum gaps can reduce the vertical electric field near the drain due to its lowest permittivity of k=1. The vacuum gaps serve as an equivalent thicker oxide. Due to the relative static permittivity SiO2 of 3.9, the equivalent oxide thickness of the vacuum gap is as high as 3.9 times [2.18]-[2.20]. The poly-Si region under vacuum gaps can be considered as the offset region and the gate edge over the vacuum cavity serves as a field plate connected with the main gate, so that the proposed TFT operates similar as the field induced drain (FID) TFTs.
2.2 Electrical Simulations for T-Gate LTPS TFTs with Vacuum Gaps
Device simulation is first carried out to compare the electric field distributions of T-Gate
TFTs with different vacuum-gap thickness (Tvac) and length (Lvac) which are followed by the experimental details of device fabrication. The 2-D numerical simulation was carried out using ISE which is a commonly used numerical simulator for device analysis [2.21].Figs. 2-2 (a) and (b) display the simulated potential contours of the proposed T-Gate and the conventional poly-Si TFTs at VGS = 1.5 V and VDS = 20 V, respectively. It can be seen evidently that in the T-Gate LTPS TFT, the electrostatic potential contours at channel surface near the drain can be relaxed remarkably by the additional offset region and vacuum gap, as compared with that in the conventional device. Under higher negative gate bias, the effective thicker gate insulator resulting from the extra vacuum gap can make less gate voltage couple to the drain junction [2.22]-[2.24].Thus, not only the maximum lateral electric field (EML) but also the maximum vertical electric field (EMV) can be effectively reduced for the proposed T-Gate poly-Si TFT.
Figs. 2-2 (a) and (b) show the 2-D electrical potential distribution of the conventional and T-Gate TFTs, respectively. The dense equi-potential lines near the drain region in conventional TFTs can be significantly relaxed in the T-Gate TFTs, indicating that electric field is consequently reduced by T-Gate structure. Figs. 2-3 (a) and (b) shows the corresponding simulated lateral and vertical electric field distributions along the channel surface near the drain junction for T-Gate TFTs with various Tvac and Lvac, respectively. The maximum lateral and vertical electric field decreases with increasing Tvac and Lvac in the T-Gate TFT. The reduction of vertical electric field is dominated by the vacuum-gap height (Tvac), while reduction of lateral electric field is dominated by the offset length (i.e. the side-etching length, Lvac).
Thus, the maximum electric field near the drain can be effectively decreased by applying
2.3 Experiments
2.3.1 Fabrication Sequence of T-Gate Poly-Si TFTs with Vacuum Gaps
The detailed process flow of device fabrication is shown in Figs. 2-4 (a)-(k). At first, a buffer layer that composed of 50nm-thick SiN and 130nm-thick SiO2 thin films was deposited by plasma-enhanced chemical vapor deposition (PECVD) system on the glass substrate. Then, a 50 nm amorphous silicon (a-Si) thin film was deposited by PECVD system on buffer layer.
Before excimer laser crystallization, dehydrogenation at 500 °C for 15 minutes was carried out to prevent the hydrogen explosion during laser irradiation. The a-Si thin film was transferred into poly-Si by 308-nm XeCl excimer laser with laser energy density of 257 mJ/cm2 and shot overlapping of 99%. After defining the active layer, a 40 nm or 80 nm-thick SiO2 was deposited as gate insulator by PECVD system at 420 °C. A 50 or 100 nm-thick indium tin oxides (ITO) and a 200 nm-thick Mo films were deposited by sputter system at room temperature sequentially. The stacked Mo/ITO films were simultaneously etched to pattern as the gate electrode. An oxalic acid, (COOH)2‧2H2O, solution was then used to selectively etch the ITO layer without harming Mo layer to form the T-shaped structure.
Different side etching lengths of ITO thin film were carefully controlled to 250 and 500 nm confirmed by the scanning electron microscope (SEM) analyses. A self-aligned phosphorous implantation was carried out to form source and drain regions with the implantation energy and dosage of 15 keV and 2 × 1014 cm-2, respectively. Then, a 500-nm-thick inter-layer dielectric of silane (SiH4)-based SiO2 was deposited by PECVD system. It should be noted that the vacuum gaps were in-situ formed during the inter-layer dielectric deposition by PECVD due to the active chemical properties of silane-based (SiH4) free radicals [2.25]. Then, the dopants were activated through rapid thermal annealing (RTA) at 620 °C for 30 seconds.
After standard contact hole opening, 500-nm-thick Al was deposited and patterned as interconnect metal. Finally, some TFTs were subjected to the NH3 plasma treatment at 300 °C for 1 hour to passivate the dangling bonds at the poly-Si/SiO2 interface and the trap-states within the poly-Si film. For the purpose of comparison, the conventional poly-Si TFTs without side-etching process shown in Fig. 2-11(l) were also fabricated with the same process sequence. For all T-Gate devices, the channel length (L) is defined as the length of the patterned Mo gate electrode, the height of vacuum gap (labeled as Tvac) is determined by the thickness of deposited ITO, and the length of vacuum gap (labeled as Lvac) is determined by the length of side-etched ITO. The split conditions of various Tvac and Lvac were designed and listed in Table 2-1. The corresponding SEM images of the fabricated T-Gate and the conventional TFTs are shown in Figs. 2-5 and 2-6, respectively.
2.4 Results and Discussion
2.4.1 Method of Electrical Parameter Extraction
In the whole thesis, all the electrical characteristics of LTPS TFTs were measured by HP 4156C semiconductor parameter analyzer. Extraction methods of all the electrical parameters mentioned in this thesis, including the threshold voltage (Vth), subthreshold swing (S.S.), maximum on-current (Ion), minimum off-current (Ioff) and the on/off current ratio, are introduced.
method, that is, defined as the gate voltage required to achieve a normalized drain current of ID = (W/L)×10-8 A at |VDS| =0.1V.
Field effect mobility (μ)
The field effect mobility is extracted from the maximum transconductance in the linear region of IDS-VGS characteristics at |VDS| = 0.1V using the formula:
, where Cox is the gate oxide capacitance per unit area, and the transconductance (gm) is defined as:
Field effect mobility is an important parameter for carrier transport; it describes how strong the motion of an electron or hole is influenced by the applied electric field.
Subthreshold swing (S.S.)
Substhreshold swing (SS) is defined as:
V
It is a typical parameter to describe the control ability of gate toward channel.
Maximum on-current and Maximum leakage-current
In this chapter, on-current is defined as the drain current measured at VGS= 15V, VDS= 3V. Maximum leakage current is defined as the drain current measured at VGS = -15V, VDS = 3V.
On/off current ratio
The on/off current ratio is defined as the ratio of maximum drain current over minimum drain current at |VDS| = 3 V.
A high performance poly-Si TFT should not only provides high on-state driving current but low off-state leakage current. High on-state driving current means the pixel capacitances could be charged more efficiently during a line access time. Sufficiently low off-state leakage current represents the charged capacitance could remain stable during the much longer frame time. Therefore, on/off current ratio is obviously a more appropriate evaluation parameter compared with on-state or off-state current alone.
2.4.2 Electrical Characteristics of T-Gate TFTs with Vacuum Gaps
Fig. 2-7 shows the transfer characteristics of T-Gate LTPS TFTs with different Tvac and fixed Lvac; while Fig. 2-8 shows those with different Lvac and fixed Tvac. All T-Gate LTPS TFTs are with channel length of 5 μm and channel width of 10 μm, and gate oxide thickness of 400 Å. It is shown that the leakage current of T-Gate LTPS TFTs could be remarkably suppressed without degrading on current significantly. It is attributed to the drain field relief via the offset region and vacuum gap to reduce the leakage current at the off state, and the low series resistance via field plate assistance to maintain the on current at the on state. The leakage current of T-Gate LTPS TFTs could also be further reduced by increasing the Tvac or Lvac due to the more vertical or lateral drain-field reduction, respectively, which is consistent with previous simulated results. For the T-Gate TFTs with Tvac = 100 nm and Lvac = 500 nm,
current ratio could be promoted to beyond 109. Table 2-2 lists the typical electrical characteristics of these devices.
In order to verify the symmetry of self-aligned ITO side etching process, the forward-mode and reverse-mode measurement were carried out, whose corresponding measurement is illustrated in Fig. 2-9. Fig. 2-10 shows the transfer characteristics of the fabricated T-Gate LTPS TFT under forward and reverse modes. There is almost no difference between these two modes, indicating that the ITO side-etching from the two sides of the patterned gate is symmetry and self-aligned.
Fig. 2-11 shows the output characteristics of T-Gate and conventional LTPS TFTs. It is shown that T-Gate LTPS TFT exhibits a reduced kink effect, while conventional LTPS TFT suffers from a severe kink at high drain biases. It is believed that the moderate kink in T-Gate LTPS TFT is mainly due to a relative low electric field near the drain junction. For conventional LTPS TFT, the severe kink at high drain biases is a result of the exaggerated avalanche multiplication near drain junction caused by the high drain field and the large amount of traps [2.26].
2.4.3 Effect of Gate Oxide Thickness
T-Gate TFTs with two different oxide thicknesses of 40 nm and 80 nm were performed to discuss the effect of gate oxide thickness. The transfer characteristics of these two kinds of T-Gate TFTs are shown in Figs. 2-12 and 2-13, respectively. The channel width and channel length were 10 μm and 5 μm. Tvac and Lvac were fixed at 100 nm and 250 nm, respectively.
The leakage current as well as the driving current at large gate bias (i.e. at VGS = -15 V and 15 V) are listed at Table 2-3. A better outcome of leakage current reduction is observed in the T-Gate TFTs with thinner gate insulator (40 nm) in comparison with the thicker one (80 nm).
Figs. 2-14 and 2-15 are the schematic illustrations of the equivalent structure of T-Gate TFTs in which the thickness of gate oxide are 40 and 80 nm, respectively. The equivalent oxide thickness at the gate edge of T-Gate TFTs with 40 nm gate oxide is 440 nm in which is 11 times the thickness of the conventional TFTs. As to the T-Gate TFTs with 80-nm-thick gate oxide, only 6 times is observed.
2.4.4 Oxide Breakdown Characteristics of T-Gate LTPS TFTs with Vacuum Gaps
Due to the low-temperature process of PECVD, the gate oxide used in LTPS TFTs usually exhibits poorer physical and electrical qualities, such as low density, high gate leakage current, and low breakdown field characteristics as compared to those high-temperature thermal grown oxide used in MOSFET technology. And, the protruded silicon surface caused from the ELA crystallization further worsens the breakdown field characteristics. To overcome this unavoidable problem, gate dielectric thin films have to be thicker to improve the poor oxide breakdown characteristics, however reducing TFT driving ability.
The gate breakdown characteristics of T-Gate and conventional TFTs with 40-nm-thick gate insulators are shown in Fig. 2-16. T-Gate TFTs with Tvac = 100 nm and Lvac = 500 nm has an excellent breakdown voltage of about 36.4 V while the conventional one has a poorer one of about 24.8 V. This is because the maximum vertical electric field between the gate edge and S/D are relaxed by the embedded vacuum in such T-Gate structure. That is, the T-Gate TFTs have a higher gate-voltage operation range than the conventional TFTs.
2.4.5 Drain Avalanche Hot Carrier (DAHC) Stress on T-Gate LTPS TFTs with Vacuum Gaps
Figs. 2-17 (a)-(c) show the transfer characteristics of conventional and T-Gate TFTs before and after drain avalanche hot carrier stress at VDS = 10 V, VGS = 1.5 V from 0 to 1000 seconds, respectively. Less degradation on transconductance, on-current and threshold voltage shift are revealed for T-Gate TFTs, while there is a serious degradation is in the conventional one. The shifts of threshold voltage, transconductance and ION were extracted in Fig.
2-18(a)-(c), respectively. Those demonstrated obviously that the T-Gate TFTs have a better immunity on drain avalanche hot carrier stress as compared to conventional one.
2.5 Summary
In this chapter, we have demonstrated high performance and high reliability T-Shaped-Gate polycrystalline silicon thin-film transistors fabricated by a low-cost process.
High-performance T-Gate TFTs with on/off ratio exceeding 109 have been demonstrated. The maximum leakage current (i.e. the drain current at VGS = -15 V and VDS = 3 V) was distinctly improved more than three orders by applying T-Gate structure. In addiction, the alleviation of kink effect was also observed due to the lower impact ionization from the proposed structure.
T-Gate LTPS TFTs with thinner oxide have better field-relief efficiency as compare to those with thicker ones. It is because the vacuum contributes more weighting in the effective oxide thickness for the thinner oxide case.
The symmetry of electrical characteristics was performed to verify that ITO side etching step was a self-aligned process. Additionally, the oxide breakdown field can be promoted
from 24.8 V to 36.4 V by adopting the T-Gate TFTs with 100-nm-thick vacuum gaps.
Moreover, T-Gate LTPS TFTs have been demonstrated to a better immunity to drain avalanche hot carrier stress.
To sum up, T-Gate structure with vacuum gaps was attractive, especially for the thin oxide devices. The characteristics of T-Gate LTPS TFTs with vacuum gaps exhibited excellent on/off current ratio. The leakage current can be decreased dramatically while the driving can be maintained. Besides, the improvement of oxide breakdown characteristics can enlarge the operation range of the gate bias. Furthermore, the proposed T-Gate TFTs have much superior immunity to the hot carrier degradation as compared with the conventional ones.
Tables
Table 2-1 Split conditions with different vacuum gap height (Tvac), side etching length (Lvac).
Table 2-2 Measured electrical characteristics of conventional and T-Gate TFTs. On current is defined as the drain current measured at VGS = 15V, VDS = 3V. Leakage-current is defined as
the drain current measured at VGS = -15V, VDS = 3V.
Conventional 1.81×10-8 2.59×10-12 4.89×10-4 1.89×108 -0.393 192
Tvac=500 Å
Conventional 1.81×10-8 2.59×10-12 4.89×10-4 1.89×108 -0.393 192
Tvac=50 nm
Lvac=250 nm 2.83×10-9 1.23×10-12 3.7×10-4 3.01×108 -0.379 201
Tvac=100 nm
Lvac=250 nm 7.45×10-11 1.4×10-13 3.21×10-4 2.29×109 -0.249 238
Table 2-3 Extraction of the leakage current and the on current at large gate bias (at VGS = -15 V and 15 V, respectively) with different gate oxide thickness. Notice that the leakage current
reduction efficiency abruptly decreased while the gate oxide thickness increased.
T
ox Structure Leakage current (A)@VGS = ‐15 V ; VDS = 3 V
On current (A)
@VGS = 15 V ; VDS = 3 V
40 nm T‐Gate TFTs 7.45E‐11
X (1/4116) 3.21E‐4
X 0.65
Conv. TFTs 1.81E‐8 4.89E‐4
80 nm T‐Gate TFTs 1.77E‐11
X (1/26) 2.06E‐4
X 0.71
Conv. TFTs 4.72E‐10 2.9E‐4
Figures
Fig. 2-1(a) The device structure of proposed T-Gate LTPS TFTs with vacuum gaps
Fig. 2-1(b) The schematic illustration of the equivalent device structure of the proposed T-Gate LTPS TFTs with vacuum gaps
(L
vac)
(T
vac)
(thicker)
Fig. 2-2(a) The 2-D electrical potential distribution of the conventional TFTs.
Fig. 2-3(a) The lateral electric fields under positive gate bias along channel layer of the conventional and T-Gate TFTs with different Tvac and Lvac.
Fig. 2-3(b) The vertical electric fields under positive gate bias along channel layer of the conventional and T-Gate TFT with different Tvac and Lvac.
6 7 8
Position along channel layer (μm) Conventional: T
Position along channel layer (μm)
Fig. 2-4 (a) Buffer layer deposition on the glass substrate
Fig. 2-4 (b) Amorphous Silicon layer deposition by PECVD system
Fig. 2-4 (c) Crystallization of the amorphous-Si film using excimer laser irradiation
Fig. 2-4 (e) Gate oxide deposition by PECVD system at 300°C
Fig. 2-4 (f) The stacked ITO/Mo layer deposition followed by patterning as the gate electrode
Fig. 2-4 (g) Selective side etching of the ITO layer to form the T-shape gate electrode structure
Fig. 2-4 (h) Self-aligned source and drain implantation to form source and drain region
Fig. 2-4 (i) Silane-base SiOx passivation layer deposition by PECVD system resulting in the in-situ vacuum gaps and then dopant activation by RTA system
Fig. 2-4 (j) Contact-hole opening and metallization
Fig. 2-4 (k) NH3 plasma passivation
Fig. 2-4(l) The conventional structure
Fig. 2-5 The SEM image of the fabricated T-Gate structure.
Fig. 2-6 The SEM image of the conventional gate electrode structure. Channel width = 10 um Channel length = 5 um Tox = 40 nm
Fig. 2-7 Transfer Characteristics of T-Gate LTPS TFTs with different Tvac and fixed Lvac, in which channel length is 5 μm, channel width is 10 μm, and the thickness of gate oxide is 40
nm.
-15 -10 -5 0 5 10 15 Channel width = 10 um Channel length = 5 um Tox = 40 nm
Fig. 2-8 Transfer Characteristics of T-Gate LTPS TFTs with different Lvac and fixed Tvac, in
Fig. 2-8 Transfer Characteristics of T-Gate LTPS TFTs with different Lvac and fixed Tvac, in