Overview of Low Temperature Polycrystalline Silicon Thin Film Transistors

During the last three decades, low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) have been increasingly used in active matrix displays, such as active matrix liquid crystal displays (AMLCDs) [1.1]-[1.7] and active matrix organic light emitting displays (AMOLEDs) [1.8]-[1.14]. In 1980s, polycrystalline silicon (poly-Si) thin film transistors (TFTs) fabricated using a maximum temperature below 600 °C commenced to study. The original motivation of this concept was to replace expensive quartz substrate with low-cost glass for active matrix display applications. This would make large-area high-resolution active matrix displays more practical and cost-effective.

In the initial stage of active matrix liquid crystal displays (AMLCDs), hydrogenated amorphous silicon (a-Si:H) TFTs were predominantly applied as the pixel switching device.

The major advantages of a-Si:H TFT technology are low processing temperature compatible with large-area glass substrate as well as its low leakage current due to the high off-state impedance. However, the low electron field-effect mobility (typically less than 1 cm²V^-1s^-1) of a-Si:H TFTs confines their application to the switching elements only. Integration of driver circuitry with display panel on the same substrate is very desirable not only to reduce the

Essentially, the effective carrier mobilities in poly-Si are significantly higher (by two orders of magnitude) than those in a-Si, so that transistors with reasonably high drive currents can be achieved in poly-Si [1.15]. The higher drive current allows smaller TFTs to be used as the pixel-switching elements, resulting in higher aperture ratio and lower parasitic gate-line capacitance for improved display performance [1.16]. In addition, the capability to realize complementary metal-oxide-semiconductor (CMOS) circuits allows low-power driver circuitry to be integrated with the active-matrix elements, for reduced display-module cost and improved reliability [1.17].

Previously, poly-Si TFT technology was primarily applied on small, high-definition LCD panels for projection display systems, because the required high processing-temperature made it incompatible with commercially available large-area glass substrates and necessitated the use of high-cost quartz substrates. In recent years, rapid progress of poly-Si has been made in the development of fabrication processes which are compatible with glass substrates and also in the improvement of process-module throughput, so that the cost-effective manufacture of LTPS TFT AMLCDs and AMOLEDs on large-area substrates increasingly flourishes.

1.2 Key Fabrication Processes of LTPS TFTs

As compared to modern complementary metal-oxide-semiconductor field-effect transistor (CMOS FET) process technology, the processes of LTPS TFTs technology only can be performed at relative low temperatures which are compatible with glass substrates. As a result, some maturely developed semiconductor fabrication processes in CMOS-FET technology cannot be applied to LTPS TFTs technology, especially on the high-temperature oxidation and dopant activation. Large-area glass substrates used in LTPS TFTs technology

also make precise lithography difficult, including fine critical dimension (CD) definition and layer-to-layer registration. Basically, all kinds of processes in the fabrication of LTPS TFTs would affect the resulting TFT performance. Other than poor crystallinity of poly-Si by nature, there are still some unique processes profoundly affecting the LTPS TFT characteristics, including crystallization of amorphous silicon (a-Si) thin films, dopant activation, defect passivation, and deposition of gate dielectric.

In the following sections, more detailed information about fabrication processes, electrical characteristics, device architectures, and applications of LTPS TFTs is introduced to give an overall concept of LTPS TFT technology.

1.3 Channel Engineering: Crystallization of Amorphous Silicon (a-Si) Thin Films

Due to the crystallized poly-Si thin films always served as channel in the poly-Si TFTs, the quality of poly-Si active layer places a profound influence on the performance of poly-Si TFTs. A good-quality poly-Si thin film always results in good electrical characteristics of poly-Si. Thus, crystallization of a-Si thin films has been considered the most important process in the fabrication of LTPS TFTs. The defect density is generally a gauge for assessing the quality of poly-Si. In polycrystalline material, most of defects are always generated in the grain boundaries and intra-grain defects. Essentially, enlarging grain size can reduce the quantity of grain boundaries. Hence, enlarging grain size can effectively promote the quality

Various technologies have been proposed for a-Si crystallization. They can be classified into two groups: solid phase crystallization and liquid phase crystallization.

In solid phase crystallization, thermal annealing provides the energy required for grain nucleation and growth. In general, intrinsic solid phase crystallization needs a long duration to fully crystallize a-Si at low temperature, and large defect density always exists in crystallized poly-Si. In liquid phase crystallization, a laser is usually employed to melting the silicon thin film.

In the following, three kinds of low temperature crystallization methods, which have been most widely studied, are roughly reviewed, including solid phase crystallization (SPC), and liquid phase crystallization.

1.3.1 Solid Phase Crystallization

Solid phase crystallization (SPC) of a-Si is a simple and effective method to acquire poly-Si thin film with large grains [1.18]. In the SPC furnace annealing, the a-Si film is annealed in a furnace for as long as 24 hours at temperatures as high as 600°C. SPC of a-Si thin films involves two distinct processes, namely the nucleation of seeds (formation of clusters of crystalline silicon) and their growth to polycrystalline films [1.19]. The transformation in the a-Si annealing proceeds after an apparent incubation period via nucleation and dendritic-like growth of crystal domain within the amorphous matrix [1.20].

The nucleations of the crystals likely occur through the thermal reaction of crystal clusters.

The rate-limiting step of the crystallization process is the rate of nucleation of seeds, which has an activation energy of about 5 eV [1.20]. The rate of the crystal growth has an activation energy of about 2.7 eV [1.20], [1.21].

Final grain size is known to be large when the nucleation rate is low and the grain growth rate is high [1.20]. Many alternatives to enlarge grain size of the annealed poly-Si thin film

are to modify the structure disorder of the starting a-Si or poly-Si thin film. Previous studies indicated that the grain size was enlarged up to a few micrometers by means of solid-state crystallization of a-Si produced by self-ion bombarded polycrystalline or amorphous films deposited by LPCVD. It is possible that ion-bombardment amorphizes the embryo of crystallines which pre-exist at the interface of the as-deposited amorphous thin films so that the incubation period of nucleation is lengthened [1.22]-[1.24]. On the other hand, it has also been reported that the grain size of the recrystallized films formed from disilane (Si2H6) is larger than that formed from silane (SiH4) [1.25]-[1.28]. The average grain size of the poly-Si thin film resulting from the crystallization of a film deposited in the amorphous phase by thermal decomposition of disilane, is a increasing function of the deposition rate, while as a function of the deposition temperature it exhibits a maximum at certain temperature (about 470°C) [1.29]. This can be attributed to the minimum nucleation rate resulting from the maximum structural disorder of the Si network. For deposition temperature higher than 470°C, the as-deposited silicon thin films have higher structural order (in the form of crystal-like clusters) which results in higher nucleation rate and thus small grain size; whereas at lower deposition temperature the higher structural disorder of the as-deposited film (or equivalently, the higher free energy) provides a driving force for accelerating the nucleation process. The increase in the grain size can also be obtained by increasing the deposition rate of the film [1.29]. Deposition rate also affects the structural order of the as-deposited film. A-Si thin films deposited at higher rates have higher structural disorder which results in lower nucleation rate during crystallization and thus larger grain size. Therefore, crystallization of a-Si thin films deposited by thermal decomposition of disilane yield very large grain size.

On the other hand, a number of researchers have examined the introduction of metal

[1.35], is deposited on a-Si, the a-Si crystallizes to poly-Si at a lower temperature than its SPC temperature. The reaction between a metal and a-Si occurs at an interlayer by diffusion and its lowers the crystallization temperature. Such enhancement of crystallization is due to an interaction of the free electrons from the metal with covalent Si bonds near the growing interface. Considering the metal-Si eutectic temperature, an a-Si thin film can be crystallized at below 500°C. A grain size up to 4-5 um has been achieved. However, with this method, the metal contamination is still an issue.

1.3.2 Liquid Phase Crystallization (Laser Crystallization)

Presently, a widely used method to prepare poly-Si on glass substrates is laser crystallization. Laser crystallization is a much faster process than SPC and MIC and can produce large grained poly-Si with a low dislocation density. The basic principle of laser crystallization is the transformation from amorphous to crystalline silicon by melting the silicon for a very short time. Poly-Si with large grains results from the subsequent solidification [1.36]. Strictly speaking, laser crystallization is not a low temperature process as the silicon is heated well above 1200 °C. However, the high temperatures are only sustained for a very short time. Due to the short time scale the thermal strain on the low-temperature substrates does not lead to severe damage or destruction of these substrates.

Laser crystallization of amorphous silicon has been a subject of intense research for a considerable time. Laser crystallization of a-Si can be performed using a variety of lasers and different techniques [1.37]-[1.40]. However, excimer laser crystallization (ELC) is by far the most widely used method at the moment [1.41], [1.42]. The principal advantage of excimer lasers is the strong absorption of UV light in silicon. In consequence, most of the laser energy is deposited close to the surface of the thin film and the thermal strain on the substrate is much lower than in case of lasers with longer wavelength. The basic transformation processes

for excimer laser crystallization are divided into three crystallization regimes depending on the applied laser fluences and are relatively well understood [1.43], [1.44].

1.3.3 Defect Passivation

Other than mentioned crystallization, the incorporation of hydrogen into the channel layer (also called hydrogenation) to passivate the defect states is effective and essential for attaining good device performance and also for improving the uniformity of device performance. The electrical behavior of a poly-Si TFT is dominated by the effects of defect states within the poly-Si thin film. The high density of defect states result in poor device performance, such as low field-effect mobility, large leakage current, large threshold voltage, and large subthreshold swing. Because significant hydrogen diffusion occurs at temperatures above 350°C, the defects passivation process must be performed after all the high-temperature-processing steps in the poly-Si TFT fabrication processes. On the other hand, it has been reported that TFTs exposed to hydrogen plasma suffer from poor hot carrier endurance and a low thermal stability due to the weak Si-H bond [1.45]. NH3 and N2 have also been proposed instead of H2. Better hot carrier endurance has been shown as the Si-N bond is stronger than Si-H bond [1.45], [1.46]. Alternative approach, which generates high-density plasma, such as ECR and TCP, may result in equivalent performance with high throughput [1.47].

For switching devices applications, the off-state leakage current of LTPS TFTs is the major concern. Although the field effect mobility of poly-Si TFTs is much higher than that of amorphous TFTs, the higher anomalous off-state leakage current in poly-Si TFTs is still an issue. The leakage currents can be reduced by either decreasing the trap state density or reducing the high electric field near the drain junction. For the driving circuit applications, the hot carriers phenomena are likely to occur in poly-Si TFTs, where supply voltages can be relatively high in the range 10-30 V [1.48]. As well known in crystalline Si (c-Si) MOSFET’s, hot carrier phenomena are strongly depended upon the maximum electric field near the drain junction [1.49]. It is worth pointing out that in poly-Si TFTs, due to the high density of trap states localized at the grain boundaries, it is possible to achieve high electric fields, even at moderate biases. Moreover, poly-Si TFTs also suffer from floating body effect due to impact ionization occurring in the high electric field region at the drain end of the channel. This effect results in an increase of the output conductance, and it is responsible for degradation of the device characteristics both in digital and in analog applications such as noise margins and available voltage gain loss [1.50].

All these undesirable effects, including off-state leakage currents, hot carrier reliability, kink effect are all related to the high electric field near the drain junction.

Drain-field-relief structures are widely adopted to solve these undesirable effects. Lightly doped drain (LDD) and offset gate are commonly used structures for reducing leakage current.

However, although the high resistivity of LDD and offset regions can effectively reduce the leakage current, unfortunately, the driving capability of TFTs is also degraded thereby. The resistivity of LDD regions depends on the length of LDD and the dose in LDD. In order to reduce leakage current without degrading driving current significantly and to get a maximum on/off current ratio, the length and dose of LDD should be carefully determined. As well as LDD structure, the length of offset region of offset gate structure should be carefully determine to keep the driving capability. Recently, advanced field-relief-structure such as field

induced drain (FID) [1.51], [1.52] and gate-overlapped LDD (GOLDD) structure has been adopted to suppress the high drain field effects for improving device reliability and reducing leakage current while a high on-state current remains. In FID structures, the offset region is coupled by a sub-gate. The sub-gate is biased to induce inversion carriers in the offset region when the TFTs operate in the on state, so that the inversion carriers contribute to a lower resistivity in on state. In GOLDD structures, the LDD region is overlapped under gate edge.

As well as FID structures, the surface of LDD region is inverted to a lower resistivity current path when the TFTs operate in the on state. A high on/off ratio can be achieved by such those advanced application because reducing leakage current while a high on-state current remains.

However, the formation of FID or GOLDD structure generally requires an additional lithography step or complex fabrication process. Besides increasing fabrication cost, the misalignment in layer registration can result in asymmetrical characteristics of TFT and poor uniformity of TFT performance, especially for large-area glass substrates.

1.5 Gate Engineering

For the consideration of low power consumption, high speed and high packing density in system on a panel, there is a need to scale down poly-Si TFTs’ device geometries However, scaling down the channel length will leads to undesirable short-channel effects. It will result in the threshold voltage roll-off, degradation in drain breakdown and severe kink effect.

Comparing with single-crystalline Si MOSFET, poly-Si TFTs show more seriously short channel effect due to the presence of rich defect in the grain boundaries which enhance the

improving the quality of poly-Si thin film. The other method is to enhance gate controllability to suppress the large filed near drain by modifying the device structures. Recently, for single-crystalline-Si MOSFETs, lots of efforts on non-planar device structures have been developed for better gate electrostatic control of the channel potential, such as double-gated, triple-gated, Π-gated, Ω-gated, nanowire channel, and GAA [1.54]-[1.58]. Among those, GAA FETs together with the nanowire channel have been reported to be the best structure for extreme geometry scaling [1.56]-[1.58].

1.6 System on a Panel (SOP) Issues

The advantages of integrating poly-Si TFTs circuits in the panel are not only it can allow pixel pitch to go beyond the bonding pitch of IC chips, but also permit to integrate a variety of circuitry not merely drivers [1.59]. However, the poly-Si TFT LCD module still costs a lot and consumes much power since it needs high driving speed and a wide voltage range analog interface [1.60]. If the TFT driver achieves full digital interface of transistor to transistor logic (TTL) or a lower voltage level, the cost of LCD module will be reduced and power consumption will be decreased.

1.6.1 Concept of System on a Panel

In short, the meaning of system on panel can be defined as the entire system integration on a single substrate including active matrix displays, integrated peripheral circuits, memory circuits, and controller circuits [1.60]-[1.63]. The first system on panel prototype was

proposed by Sharp Corp. and Semiconductor Energy Laboratory Co. in 2004, which realizes the integration of CPU, an audio circuit, a graphic controller, and memories on the liquid crystal display by continuous grain silicon (CGS) technology. CG silicon fabricated in low temperature by catalyst assists solid phase crystallization, which doesn’t subject to the effects of variations in laser density [1.64]. This crystallization method offers superior reliability and uniformity. The 8-bit CPU contains about thirteen thousand TFTs and operates at 3MHz with 5V voltage supply.

Various kinds of voltage or signal losses come into existence in the module because the system has to transfer enormous data between the large scale circuits at high frequency [1.60].

If the large scale circuits can be entirely integrated in the same substrate without sacrificing functional properties, the total performance will be improved and the power consumption will be diminished theoretically. More importantly, the size, weight, and cost of the system will be cut down which is beneficial to the consumers.

There are two main considerations to achieve the goal of system on panel. First, the properties of poly-Si TFTs must be improved such as better mobility (larger than 400 cm²/Vs), shorter channel device (less than 1 μm), lower sub-threshold swing (~0.1 V/dec), lower threshold voltage(~±0.7 V), higher on/off current ratio (~10⁹) are needed. Second, the circuit interconnection technique needs to be promoted. When shrinking the transistor size, excellent uniformity and reliability are critically required for the development of SOP.

1.7 Motivation

displays, such as active matrix liquid crystal displays (AMLCDs) [1.1]-[1.7] and active matrix organic light emitting displays (AMOLEDs) [1.8]-[1.14], and potential for 3-dimension ICs’

applications [1.65]. The ability of fabricating high-performance LTPS TFTs enables their use in further applications of SOPs. Therefore, there is great interest in improving the performance of LTPS TFTs. Considering the issues of system on panel (SOP) mentioned in former section, both the LTPS TFT performance and the added-value functionality need to be further promoted and developed. For the further development, high versatile circuits and systems need to be fully integrated to achieve system-on-panel (SOP). As performance and complexity requirements increase, there is a need to scale down device geometries to achieve higher speeds and packing densities. Unfortunately, those undesirable effects in the electrical characteristics that mentioned above become particularly important as the channel length and gate insulator thickness are reduced. Those all are increased with the higher drain electric field near the drain junction. These undesirable effects prohibit the use of poly-Si TFTs in many high-performance circuit applications. Therefore, the drain-field-relief structure plays

applications [1.65]. The ability of fabricating high-performance LTPS TFTs enables their use in further applications of SOPs. Therefore, there is great interest in improving the performance of LTPS TFTs. Considering the issues of system on panel (SOP) mentioned in former section, both the LTPS TFT performance and the added-value functionality need to be further promoted and developed. For the further development, high versatile circuits and systems need to be fully integrated to achieve system-on-panel (SOP). As performance and complexity requirements increase, there is a need to scale down device geometries to achieve higher speeds and packing densities. Unfortunately, those undesirable effects in the electrical characteristics that mentioned above become particularly important as the channel length and gate insulator thickness are reduced. Those all are increased with the higher drain electric field near the drain junction. These undesirable effects prohibit the use of poly-Si TFTs in many high-performance circuit applications. Therefore, the drain-field-relief structure plays