Summary - Impacts of Buffer Layer on the Performance and Reliability of

Chapter 2 Impacts of Buffer Layer on the Performance and Reliability of

2.4 Summary

The effects of LPCVD SiN capping and the associated deposition process on the device performance and hot-carrier degradation were investigated in this work. A novel scheme involving the insertion of a buffer layer between the SiN and the gate for improving the device reliability was proposed and demonstrated. We found that the 20 nm-thick buffer layer does not compromise the mobility enhancement due to the SiN capping, while the device performance enhancement starts to diminish if the thickness of the buffer layer exceeds 30 nm.

The accompanying bandgap narrowing effect and the increased carrier mobility tend to worsen the hot-carrier reliability. This work confirms that hot-carrier

degradation is adversely affected when the SiN layer is deposited over the gate, even if the SiN layer is removed later and the channel strain is relieved. Abundant hydrogen species incorporated into the channel region during the SiN deposition process, owing to the use of hydrogen-containing precursors, is the primary culprit for aggravated reliability. By blocking the diffusion of hydrogen species, the devices with 20 nm-thick TEOS buffer layer can effectively improve the hot-carrier reliability without degrading the performance enhancement. Optimizations of both the SiN deposition process and the use of the new buffer layer (e.g., high-k film) are thus essential to the implementation of the uniaxial strain in NMOS devices.

References

[1] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, D. A. Antoniadis, “Strained Silicon MOSFET Technology,” IEDM Tech. Dig., pp.

23-26, 2002.

[2] B. H. Lee, A. Mocuta, S. Bedell, H. Chen, D. Sadana, K. Rim, P. O’Neil, R. Mo, K.

Chan, C. Cabral, C. Lavoie, D. Mocuta, A.Chakravarti, R. M. Mitchell, J.

Mezzapelle, F. Jamin, M. Sendelbach, H. Kermel, M.Gribelyuk, A. Domenicucci, K. A. Jenkins, S. Narasimha, S. H. Ku, M. Ieong, I. Y. Yang, E. Leobandung, P.

Agnello, W. Haensch, and J. Welser, “Performance Enhancement on Sub-70nm Strained Silicon SOI MOSFETs on Ultra-thin Thermal Mixed Strained Silicon/SiGe on Insulator (TM-SGOI) Substrate with Raised S/D,” IEDM Tech.

Dig., pp. 946-948, 2002.

[3] X. Chen, S. Fang, W. Gao, T. Dyer, Y. Ko, C. Baiocco, A. Ajmera, J. Park, J. Kim, D. Chidambarrao, Z. Luo, N. Nivo, P. Nguyen, S. Panda, O. Kwon, N. Edleman, M. Belyansky, R. Amos, H. Ng, M. Hierlemann, D. Coolbough, T. Schiml, J. H.

Ku, and C. Davis, “Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond,” Proc. Symp. VLSI Technology, pp. 60-11, 2005.

[4] K. Uejima, H. Nakamura, T. Fukase, S. Mochizuki, S. Sugiyama, and M. Hane,

“Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration,” Proc. Symp. VLSI Technology, pp. 220-221, 2007.

[5] K. W. Ang, K. J. Chui, H. C. Chin, Y. L. Foo, A. Du, W. Deng, M. F. Li, G.

Samudra, N. Balasubramanian, and Y. C. Yeo, “50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Regions and Tensile Stress Silicon Nitride Liner,” Proc. Symp. VLSI Technology, pp. 90-91,

2006.

[6] Y. Liu, O. Gluschenkov, J. Li, A. Madan, A. Ozcan, B. Kim, T. Dyer, A.

Chakravarti, K. Chan, C. Lavoie, I. Popova, T. Pinto, N. Rovedo, Z. Luo, R.

Loesing, W. Henson, and K. Rim, “Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy,” Proc. Symp. VLSI Technology, pp. 44-45, 2007.

[7] K. Ota, T. Yokoyama, H. Kawasaki, M. Moriya, T. Kanai. S. Takahashi, T.

Sanuki, E. Hasumi, T. Komoguchi, Y. Sogo, Y. Takasu, K. Eda, A. Oishi, K.

Kasai, K. Ohno, M. Iwai, M. Saito, F. Matsuoka, N. Nagashima, T. Noguchi, and Y. Okamoto, “Stress Controlled Shallow Trench Isolation Technology to Suppress the Novel Anti-Isotropic Impurity Diffusion for 45nm-node High Performance CMOSFETs,” Proc. Symp. VLSI Technology, pp. 138-139, 2005.

[8] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R.

Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M.

Kase, and K. Hashimoto, “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile and High Compressive Silicon Nitride Films,”

IEDM Tech. Dig., pp. 213-216, 2004.

[9] K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A.

Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson and M.

Bohr, “Delaying Forever: Uniaxial Strained Silicon Transistors in A 90nm CMOS Technology,” Proc. Symp. VLSI Technology, pp. 50-51, 2004.

[10] C. H. Chen, T. L. Lee, T. H Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M.-S. Liang, “Stress Memorization Technique (SMT) by Selectively Strained-nitride Capping for Sub-65nm High-performance Strained-Si Device Application,” Proc. Symp. VLSI

Technology, pp. 56–57, 2004.

[11] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key Differences for Process-Induced Uniaxial vs. Substrate-Induced Biaxial Stressed Si and Ge Channel MOSFETs,” IEDM Tech. Dig., pp. 221-224, 2004.

[12] E. Li, E. Rosenbaum, J. Tao, and P. Fang, “Projecting Lifetime of Deep Submicron MOSFETs,” IEEE Trans. on Electron Devices, vol. 48, no. 4, pp. 671-678, 2001.

[13] H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, “A Study of Hot-carrier Degradation in N- and P-MOSFETs with Ultra-thin Gate Oxides in the Direct-Tunneling Regime,” IEDM Tech. Dig., pp. 453-456, 1997.

[14] S. Dey, M. Agostinelli, C. Prasad, X. Wang, and L. Shifren, “Effects of Hot Carrier Stress on Reliability of Strained-Si MOSFETs,” Proc. Int. Reliability Physics Symp., pp.461-464, 2006.

[15] R. B. Fair, and R. C. Sun, “Threshold-Voltage Instability in MOSFET's due to Channel Hot-Hole Emission,” IEEE Trans. on Electron Devices, vol. 28, no. 1, pp.

83-94, 1981.

[16] M. Shimaya, “Water Diffusion Model for the Enhancement of Hot-Carrier-Induced Degradation due to Silicon Nitride Passivation in Submicron MOSFETs,” Proc. Int. Reliability Physics Symp., pp.292-296, 1995.

[17] A. Schwerin, W. Hansch, and W. Weber, “The Relationship Between Oxide Charge and Device Degradation: A Comparative Study of N- and P-Channel MOSFETs,” IEEE Trans. on Electron Devices, vol. 34, no. 12, pp. 2493-2500, 1987.

[18] P. Heremans, R. Bellens, G. Groeseneken, and H. Maes, “Consistent Model for the Hot-carrier Degradation in N- and P-Channel MOSFETs,” IEEE Trans. on

Electron Devices, vol. 35, no. 12, pp. 2194-2209, 1988.

[19] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T.

Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.

Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S.

Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy,

“A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, 2004.

[20] C. Y. Lu, H. C. Lin, Y. F. Chang, and T. Y. Huang, “Devices Characteristics and Aggravated Negative Bias Temperature Instability in PMOSFETs with Uniaxial Compressive Strain,” Jan. J. Appl. Phys., vol. 45, pp. 3064-3069, 2006.

[21] M. Lenzlinger, and E. H. Snow, “Fowler-Nordheim Tunneling into Thermal Grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278-283, 1969.

[22] P. Olivo, J. Sune, and Bruno Ricco, “Determination of the Si-SiO2 Barrier Height form the Fowler-Nordheim Plot,” IEEE Electron Device Lett., vol. 12, no. 11, pp.

620-622, 1991.

[23] A. Gupta, P. Fang, M. Song, M. R. Lin, D. Wollesen, K. Chen, and C. Hu,

“Accurate Determination of Ultratin Gate Oxide Thickness and Effective Polysilicon Doping of CMOS Devices,” IEEE Electron Device Lett., vol. 18, no.

12, pp. 580-582, 1997.

[24] J. S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M.

R. Lin, “Band Offset Induced Threshold Variation in Strained-Si NMOSFETs,”

IEEE Electron Device Lett., vol. 24, no. 9, pp. 568-570, 2003.

[25] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of Threshold Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed N-MOSFETs” IEEE Electron Device Lett., vol. 25, no. 11, pp. 731-733, 2004.

[26] T. Hoshii, S. Sugahara, and S. Takagi, “Effect of Tensile Strain on Gate and Substrate Currents of Strained-Si N-MOSFETs,” Int. Conference on Solid State Devices and Materials, pp. 164-165, 2006.

[27] H. I. Hanafi, W. P. Noble, R. S. Bass, K. Varahramyan, Y. Lii, and A. J. Dally, “A Model for Anomalous Short-Channel Behavior in Submicron MOSFETs,” IEEE Electron Device Lett., vol. 14, no. 12, pp. 575-577, 1993.

[28] N. Sano, M. Tomizawa, and A. Yoshii, “Temperature Dependence of Hot Carrier Effects in Short-Channel Si-MOSFETs”, IEEE Trans. on Electron Devices, vol. 42, no. 12, pp. 2211-2216, 1995.

[29] M. F. Lu, S. Chiang, A. Liu, S. H. Lu, M. S. Yeh, J. R. Hwang, T.H. Tang, W.T.

Shiau, M. C. Chen and T. Wang, “Hot Carrier Degradation in Novel Strained-Si NMOSFETs,” Proc. Int. Reliability Physics Symp., pp. 18-22, 2004.

[30] C. Y. Lu, C. S. Lu, Y. L. Hsieh, Y. J. Lee, H. C. Lin, and T. Y. Huang, “Impacts of LP-SiN Capping Layer and Lateral Distribution of Interface Trap on Hot Carrier Stress of NMOSFETs,” Int. Conference on Solid State Devices and Materials, pp.528-529, 2006.

[31] W. B. Jackson, N. M. Johnson, C. C. Tsai, I. W. Wu, A. Chiang, and D. Smith,

“Hydrogen Diffusion in Polycrystalline Silicon Thin Films,” Appl. Phys. Lett., vol.

61, no. 14, pp.1670-1672, 1992.

[32] N. H. Nickel, W. B. Jackson, and J. Walker, “Hydrogen Migration in Polycrystalline Silicon,” Physical Review B, vol. 53, no. 12, pp. 7750-7761, 1996.

[33] C. Chen and T. P. Ma, “Direct Lateral Profile of Hot-Carrier-Induced Oxide Charge and Interface Traps in Thin Gate MOSFET’s,” IEEE Trans. on Electron Devices, vol.45, no. 2, pp.512-520, 1998.

[34] M. Tsuchiaki, H. Hara, T. Morimoto, and H. Iwai, “A New Charge Pumping

Method for Determining the Special Distribution of Hot-Carrier-Induced Fixed Charge in P-MOSFETs,” IEEE Trans. Electron Devices, vol. 40, no. 10, pp.

1768–1778, pp.1768-1778, 1993.

Fig. 2.1(a) Cross-sectional TEM pictures for SiN-capped samples.

1894Å

3178Å

400Å 1516Å

~30Å

SiN-capped

Fig. 2.1(b) Cross-sectional TEM pictures for control samples.

1442Å

405Å

1924Å

Control

Fig. 2.1(c) Cross-sectional TEM pictures for BL-10nmTEOS samples.

1935Å

3194Å

~96Å

1467Å

BL-10nmTEOS

Fig. 2.1(d) Cross-sectional TEM pictures for BL-20nmTEOS samples.

3143Å 2104Å

1481Å

~200Å

BL-20nmTEOS

Fig. 2.1(e) Cross-sectional TEM pictures for BL-10nmPOLY samples.

1453Å 3093Å

1930Å

116Å

BL-10nmPOLY

Fig. 2.1(f) Cross-sectional TEM pictures for BL-20nmPOLY samples.

3202Å

1478Å 2098Å

197Å

BL-20nmPOLY

V

-V

_th

(V)

Fig. 2.2 NMOSFETs subthreshold characteristics and transconductance for all seven splits. The subthreshold swing is nearly identical among the seven splits, while the transconductance is obviously larger for the SiN-capped and all buffer layer samples.

Control

SiN-Capped

BL-10nmTEOS

BL-20nmTEOS

BL-10nmPOLY

SiN Removal

Subthreshold Swing (mV/dec)

70 72 74 76 78 80

W/L=10/0.4μm

Fig. 2.3 Subthreshold swing of NMOSFETs for all splits of samples with W/L = 10/0.4 μm

Drain Voltage (V)

0.0 0.5 1.0 1.5 2.0

Drain Current (mA)

0 1 2 3 4 5 6

7

Control

SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

Vg - Vt = 0.4V Vg - Vt = 1.2V

Vg - Vt = 2V

W/L=10/0.4μm

Fig. 2.4 Output characteristics of NMOSFETs for all splits.Drive current enhancement is clearly observed for the SiN-capped and all buffer layer splits. The SiN-removal samples show negligible enhancement.

Channel Length (μm)

1 10

Δ Gm

max

/Gm

max

(%)

0 10 20 30 40

SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

Fig. 2.5 Percentage increase of transconductance versus channel length for all splits of samples with respect to the control ones. Each datum point represents the mean measurement result performed on six devices.

Gate Voltage (V)

-2 -1 0 1

Capacitance ( μF/cm

)

0.2 0.4 0.6 0.8 1.0

1.2

Control

SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

W/L=50/50μm

Tox,inv ~ 3.85nm

Fig. 2.6 Capacitance-Voltage (C-V) characteristics for all seven splits. Basically the seven splits show almost identical curve, indicating that the oxide thickness difference among these seven splits is negligible.

Fig. 2.7 Energy band diagram illustrating F-N tunneling.

p-type substrate

SiO₂ n⁺-poly

qφB

qVox

Ec Ev

Ec EF Ev

Gate Voltage (V)

4.5 4.6 4.7 4.8 4.9 5.0

Gate Current Density (A/cm 2 )

10

^-2

10

^-1

10

⁰

Control J_FN Fitting

W/L=10μm/0.5μm T_ox=2.919nm

Fig. 2.8 The plot of JG versus VG for control samples. The extracted oxide thickness by F-N current fitting is about 2.919 nm.

1/E

_ox

(cm/V)

7.5e-8 8.0e-8 8.5e-8

ln(J

/E

ox2

)

-36.0 -35.5 -35.0 -34.5 -34.0 -33.5 -33.0

Control

W/L=10μm/0.5μm

Control φB=3.03 eV slop=2.55x108

Fig. 2.9 F-N plot for control samples. The extracted barrier height is about 3.03 eV.

Gate Voltage (V)

4.6 4.7 4.8 4.9 5.0

Gate Current Density (A/cm

)

10

^-2

10

^-1

10

⁰

Control Tox=2.919nm SiN-Capped Tox=2.933nm BL-10nmTEOS Tox=2.932nm BL-20nmTEOS Tox=2.935nm BL-10nmPOLY Tox=2.933nm BL-20nmPOLY Tox=2.934nm SiN Removal Tox=2.919nm

W/L=10μm/0.5μm

Fig. 2.10 The plot of JG versus VG for all splits.

Tox (nm)

2.90 2.91 2.92 2.93 2.94 2.95

φ

(eV )

3.00 3.02 3.04 3.06 3.08 3.10 3.12 3.14 3.16

Control SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

Strain

no Strain

~100meV

Fig. 2.11 The extracted barrier height versus gate oxide thickness for all splits. We can see that the barrier heights for all SiN capping samples are larger than control ones.

Tox (nm)

4.30 4.35 4.40 4.45 4.50

φ

(eV )

3.06 3.08 3.10 3.12 3.14 3.16 3.18 3.20 3.22

Control SiN Capping

Strain

no Strain

~100meV

Fig. 2.12 The extracted barrier height for thicker gate oxide thickness (~4.3 nm). The barrier height for non-strained samples is close to 3.1 eV, while the SiN capping samples still exhibit barrier height increased of about 100 meV.

Channel Length (μm)

1 10

Δ V

(mV)

-120 -100 -80 -60 -40 -20 0 20 40

Control SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY

SiN Removal

Fig. 2.13 Threshold voltage roll-off characteristics as a function of channel length for all splits of samples.

Gate Length (μm)

1 10

DIBL (mV/V)

2 4 6 8 10 12 14 16 18 20

Control SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

Fig. 2.14 Drain induced barrier lowering (DIBL) characteristics as a function of channel length for all splits of samples.

Gate Voltage (V)

1.0 1.5 2.0 2.5 3.0

Substrate Current (-mA)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Control SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

V_DS = 4.9V W/L=10/0.5μm

Fig. 2.15 Substrate current versus gate voltage for all splits of samples with W/L = 10/0.5 μm.

Gate Voltage (V)

Fig. 2.16 (a) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for control samples.

Gate Voltage (V)

Fig. 2.16 (b) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for SiN-capped samples.

Gate Voltage (V)

Fig. 2.16 (c) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for BL-10nmTEOS samples.

Gate Voltage (V)

Fig. 2.16 (d) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for BL-20nmTEOS samples.

Gate Voltage (V)

Fig. 2.16 (e) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for BL-10nmPOLY samples.

Gate Voltage (V)

Fig. 2.16 (f) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for BL-20nmPOLY samples.

Gate Voltage (V)

Fig. 2.16 (g) Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for SiN-removal samples.

Stress Time (sec)

0 1000 2000 3000 4000 5000 6000

Δ V

(mV)

0 50 100 150 200 250

300

^Control_SiN-Capped

BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

W/L=10/0.5μm VDS = 4.9V, V^G@I_sub,max

Fig. 2.17 Threshold voltage shift as a function of stress time. Devices with W/L = 10/0.5 μm were stressed at VDS = 4.9 V, and VG of maximum substrate current. Each datum point represents the mean measurement results performed on three devices.

Fig. 2.18 (a) In SiN-capping devices, a large amount of hydrogen species from the SiN layer diffuse to the gate oxide layer and the channel region through three possible pathways. (b) In the devices with buffer layer, the diffusion of hydrogen species can be suppressed by the buffer layer.

H H

Base Voltage (V)

-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2

Charge Pumping Current (nA) 0.0

0.1 0.2 0.3 0.4

SiN Capping BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY

W/L=10/0.5μm

Fig. 2.19 Charge pumping current for all SiN capping samples with or without buffer layer with W/L = 10/0.5 μm.

Fig. 2.20 Single junction charge pumping measurement setup.

Floating Icp

Drain Source

Gate

Fixed base mode Vbase = -1V,

V_h = -0.8V ~ 1V

V

_base

V

Fig. 2.21 Nonuniform distribution of local threshold voltage and flat band voltages across device caused by variation in lateral doping concentration.

Vth

Vfb

Vbase

Drain Source

Gate

Peak Voltage (Vh) (V)

-0.5 0.0 0.5 1.0

Icp (pA)

0 20 40 60 80

x ( μm)

0.0 0.1 0.2 0.3 0.4

W/L=10/0.5μm Icp,max 0.5

Vth(x)

Fig. 2.22 Derived relationship between local threshold voltage and lateral distance x from single junction charge pumping data of control device.

x (μm)

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Local Threshold Voltage (V)

-0.4 -0.2 0.0 0.2 0.4

W/L=10/0.5μm

Fig. 2.23 Extracted lateral profile of local threshold voltage near graded drain junction in control sample.

Peak Voltage (Vh) (V)

-0.5 0.0 0.5 1.0

Ic p (p A)

0 100 200 300 400 500

Fresh Stressed

ΔIcp

Fig. 2.24 Charge pumping current before and after 100 s hot-carrier stressing (VG at Isub,max and VDS = 4.9V) with W/L = 10/0.5 μm.

Fig. 2.25 Lateral profile of interface state generation after hot-carrier stress for all splits of samples.

x (μm)

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Generated Interface Trap (10 10 cm -2 )

0 20 40 60 80 100 120 140

Control SiN-Capped BL-10nmTEOS BL-20nmTEOS BL-10nmPOLY BL-20nmPOLY SiN Removal

W/L=10/0.5μm

Drain edge

Center

V

-V

_th

(V)

Fig. 2.26 NMOSFETs subthreshold characteristics and transconductance for control, SiN-capped, BL-10nmTEOS, BL-30nmTEOS, and BL-50nmTEOS splits. The transconductance enhancement starts to diminish for BL-30nmTEOS split.

Stress Time (sec)

0 1000 2000 3000 4000 5000

Δ V

(mV)

0 20 40 60 80 100 120 140 160 180

SiN Capping BL-10nmTEOS BL-30nmTEOS BL-50nmTEOS

W/L=10μm/0.5μm

VDS = 4.6V, V^G@I_sub,max

Fig. 2.27 Threshold voltage shift as a function of stress time. Devices with W/L = 10/0.5 μm were stressed at VDS = 4.6 V, and VG of maximum substrate current.

Chapter 3 Optimization of SiN Deposition Conditions and Its Impacts on Strained n- and p-Channel MOSFETs

3.1 Introduction

Channel strain engineering such as embedded SiC source/drain (S/D) [1-2] and highly tensile SiN capping layer [3-4,10-13] for n-channel metal-oxide-semiconductor field-effect-transistors (NMOSFETs) or embedded SiGe S/D [5-8] and highly compresseive SiN capping layer [7-9] for PMOSFETs has been pursued aggressively for mobility enhancement in scaled complementary metal-oxide-semiconductor (CMOS) devices. Among these methods, SiN capping technique has received much attention because it is easily implemented in modern VLSI technology. In addition, depending on the SiN deposition conditions, stress from highly tensile to highly compressive is adjustable, enabling the dual-SiN stressor technology for CMOS manufacturing [10].

Although SiN capping can dramatically enhance the device performance, the abundant hydrogen species generated during the SiN deposition process may diffuse into the channel region, resulting in aggravated hot-carrier degradations [11]. Recently, the insertion of an ultra-thin buffer layer underneath the SiN capping layer has been proposed to suppress the hydrogen diffusion and restore the reliability without compromising device performance [12-13]. In this thesis, another useful approach to directly adjust the composition of SiN film by varying precursor gas flow rate and deposition temperature is explored. Our results indicate that it is indeed possible to alleviate the dramatic aggravation of device reliability without compromising the device performance caused by the channel strain.

3.2 Devices Fabrication

The NMOSFETs characterized in this study were fabricated on 6-inch p-type (100) Si wafers with conventional local oxidation of silicon (LOCOS) isolation. The 3 nm-thick thermal oxide was grown in a vertical furnace, followed by the deposition of a 150nm-thick polycrystalline-silicon (poly-Si) layer to serve as the gate electrode. After S/D doping and self-aligned spacers formation steps, rapid thermal anneal (RTA) was then carried out in a nitrogen ambient at 900°C for 30 sec to activate dopants in the gate and S/D junctions. Afterwards, a 300nm-thick SiN capping layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) system. The schematic structure of the fabricated device was shown in Fig. 3.1. In this work, we evaluated devices with five different types of SiN film using SiH4/NH3/N2 gas mixtures at either 300°C or 400°C (denoted as SiN-1, SiN-2, SiN-3, SiN-1(400°C), and SiN-3(400°C) splits, respectively). The detailed gas flow rates are listed in Table 3-I, and the major parameter adjusted was the N2 gas flow rate. Deposition pressure and rf power were fixed at 1 Torr and 100W, respectively. In addition to SiN-capped samples, the control devices with 300nm-thick PECVD oxide were also fabricated for comparison purpose (denoted as SiO2 split).

On the other hand, the PMOSFETs were also fabricated on 6-inch n-type (100) Si wafers with LOCOS isolation, and have 3nm-thick gate oxide and 150nm-thick poly-Si gate electrode. After standard procedures to form TEOS spacers, S/D junction, and RTA anneal, the devices were capped with a 300 nm-thick PECVD oxide, SiN-1 film, and SiN-3 film (as described in Table 3-I), denoted as p_SiO2, p_SiN-1, and p_SiN-3 splits, respectively. After contact hole and metallization processes, the processing steps were completed with a forming gas anneal at 400°C. Electrical characteristics were performed using an Agilent 4156 system. The interface traps were evaluated using the

charge pumping method with a fixed amplitude of 1.5V at 1 MHz.

3.3 Results and Discussion

3.3-1 Material Analysis

X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared spectrometer (FTIR) were employed to investigate the material properties of the deposited SiN films. Major results are given in Fig. 3.2 and Fig. 3.3, respectively. From XPS analysis, as shown in Fig. 3.2(a), we confirmed that the SiN-3 split contains higher N content than the other samples. Obviously the use of higher N2 flow rate in the deposition process is responsible for the finding. When the deposition temperature is raised to 400°C, as shown in Fig. 3.2(b), we can see that the SiN-1(400°C) and SiN-3(400°C) samples depict similar trend with the SiN-1 and SiN-3 splits, respectively, implying that N content in the SiN film does not seem to be affected by the temperature of 400°C. In addition, Figure 3.3 shows the analysis of FTIR measurement. It can be seen that the SiN-1 split contains the largest amount of Si-H bonds among all splits, while increase in N2 flow rate (shown in SiN-3 split) [14] and deposition temperature (shown in SiN-1(400°C) and SiN-3(400°C) splits) [15] tend to weaken the signal of Si-H bonds. Later we will show that this finding is important for robusting the immunity of devices to hot-carrier and NBTI degradations.

Besides, mechanical stress was also investigated in this work. The stress measurements were performed on a Tencor FLX-2320 system. This system evaluates the stress by measuring the change in curvature of the silicon substrate before and after deposition of a blanket SiN layer with a thickness of 300 nm. We confirmed that the stress is tensile in nature with the magnitude of around 127, 344, 556, 96, and 576 MPa for SiN-1, SiN-2, SiN-3, SiN-1(400°C), and SiN-3(400°C) splits, respectively, as listed

in Table 3-I. It can be seen that the tensile stress increases with increasing N2 flow rate, as shown in Fig. 3.4, while it is only mildly affected by the two deposition temperatures studied in this work.

3.3-2 Devices Characteristics for NMOSFETs

Next, the electrical characteristics were performed using an Agilent 4156 system.

Figure 3.5 compares transconductance (Gm) enhancement for all splits with channel width/length (W/L) = 10/0.4 μm. It can be seen that SiN-3 and SiN-3(400°C) splits depict the largest and identical Gm among all samples, while the SiN-1 and SiN-1(400°C) splits show comparable Gm with the SiO2 split, and the SiN-2 split falls between these two groups. Similar enhancement trend in drive current is also observed, as shown in Fig. 3.6. These electrical results are consistent with the results of film stress measurement listed in Table 3-I. Figure 3.7 shows the Gmmax as a function of tensile stress with W/L = 10/0.4 μm for all SiN-capping samples. Gmmax increases with increasing tensile stress, and a linear dependence is observed in this figure.

在文檔中具有氮化矽覆蓋之形變通道金氧半場效電晶體特性與相關可靠性問題研究 (頁 57-0)