Chapter 1 Introduction
1.3 Thesis Organization
This dissertation is divided into seven chapters.
In Chapter 1, the backgrounds and motivations of the thesis are reviewed.
In Chapter 2, a novel scheme involving the insertion of a thin buffer layer between the gate and the SiN layer is proposed and demonstrated to restore the hot-carrier reliability of the SiN-capped devices without compromising the current enhancement
due to the SiN capping. Bandgap narrowing effect induced by SiN capping and the lateral distribution of interface state after hot-carrier stress are also investigated.
In Chapter 3, the strained n- and p-channel MOSFETs with different types of SiN film by varying the N2 flow rate and deposition temperature during the deposition step are fabricated and characterized. X-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectrometer (FTIR), and film stress measurement system are applied to analyze the properties of the SiN films. We found that tensile stress increases with increasing N2 flow rate, therefore boosting the NMOSFETs’ performance. In addition, the increase in N2 flow rate and deposition temperature tends to weaken the signal of Si-H bonds. Finally, the immunity for devices to hot-carrier degradation and NBTI reliability is mainly affected by the hydrogen content, rather than the stress level.
In Chapter 4, we have fabricated strained-channel NMOSFETs with different tensile stress by adjusting SiN thickness. The impacts of stress induced by SiN capping on the leakage current are investigated. Gate-induced drain leakage (GIDL) current is identified to be responsible for increased off-state leakage current.
In Chapter 5, SiN-capped PMOSFETs with a thin HfO2 buffer layer were fabricated and characterized. HfO2 buffer layer is helpful to mitigate the degradation of NBTI. In addition, AC NBTI stress of devices is further studied. The aggravated NBTI degradation in the SiN-capped devices can be alleviated by high frequency operation, while HfO2-buffered sample still depicts less degradation than SiN-capped sample.
In Chapter 6, the impacts of devices with SiN capping layer on the flicker noise characteristics are investigated. Both carrier number fluctuation theory and mobility fluctuation theory are utilized to model the flicker noise. We found that hydrogen species contained in the SiN film play an important role in the flicker noise characteristics.
In Chapter 7, we conclude with summaries of the experimental results.
Recommendations for future research are also given.
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Table 1-I Impacts of 3D strain direction on device performance. X represents the longitudinal direction of carrier transport, Y represents the in-plane transverse direction of carrier transport, and Z represents the direction of out-of-plane. [18]
Increasing Tensile Stress Strain Direction
NMOSFET PMOSFET
X Improve Degrade
Y Improve Improve
Z Degrade Improve
Chapter 2
Impacts of Buffer Layer on the Performance and Reliability of Strained Channel NMOSFETs with SiN Capping
2.1 Introduction
Channel-strain engineering has emerged as one of the most effective remedies for boosting the drive current in the scaled devices [1-11]. This could be accomplished by either applying high biaxial tensile strain to the channel region with a SiGe virtual substrate [1-2], or by uniaxially straining the channel with strain boosters, such as stress liner [3-4], embedded SiC in the source/drain (S/D) [5-6], and shallow trench isolation [7]. The approach of using SiGe virtual substrate, however, suffers from a number of drawbacks such as Ge up-diffusion and high defect density. In contrast, the approach of uniaxially straining the channel is essentially free from the aforementioned drawbacks.
Capping a tensile-strain SiN layer over the gate of NMOSFETs as contact etch-stop layer (CESL) has been shown to enhance drive current by improving channel mobility [8-11]. Such scheme is attractive and practical because it can be easily implemented using integrated circuit processing.
Nevertheless, with the demonstrated performance improvement, attentions should now be paid to the associated reliability issues for practical applications. Currently, device degradation caused by hot-carriers represents one of the most critical reliability issues in deep sub-micron NMOSFETs [12-14]. Although the physical mechanisms and characteristics of hot-carrier degradation have been extensively examined [15-18], there seems to be very few works investigating the impact of SiN capping and the associated deposition process on hot-carrier reliabilities of strained devices. Furthermore, the effect
of capping a buffer layer prior to the SiN layer has not been reported in literature. In this thesis, we have investigated this issue and demonstrated that the incorporation of a thin TEOS or poly-Si buffer layer over the gate could improve the device reliability without compromising the performance enhancement by the SiN capping. In addition, the barrier height at the Si/oxide interface for strained channel devices and lateral distribution of interface state after hot-carrier stress were also investigated.
2.2 Devices Fabrication
The NMOSFETs were fabricated on 6-inch p-type (100) Si wafers with conventional local oxidation of silicon (LOCOS) isolation. Gate oxide with a thickness of 3 nm was grown in vertical furnace in O2 at 800˚C. After gate oxide growth, 150 nm poly-Si layer was deposited by a low-pressure chemical vapor deposition (LPCVD) system to serve as the gate electrode. After As+ implantation (at 20 KeV and 5×1015 cm-2), 40 nm TEOS was deposited to serve as as hard mask. An I-line stepper was used to define the gate. Afterwards, standard procedures were applied to form TEOS spacer and S/D junction. Dopant activation was performed at 900˚C for 30 sec.
Afterwards, most wafers were capped with a 300nm-thick SiN layer (denoted as the SiN-capped split). While for some other wafers, a thin LPCVD TEOS or undoped poly-Si buffer layer, with a thickness of either 10 nm or 20 nm, were capped prior to the SiN deposition (denoted as the BL-10nmTEOS, BL-20nmTEOS, BL-10nmPOLY, and BL-20nmPOLY splits, respectively). The SiN deposition was performed at 780˚C with SiH2Cl2 and NH3 as the reaction precursors using LPCVD system. To simulate the effect of deposition temperature during the SiN deposition, the control devices (i.e., without SiN capping) received a placebo treatment (i.e., the same temperature and treatment time as that used in the SiN deposition) in the N2 ambient.
In some of the SiN-capped wafers, the SiN layer was deliberately removed after deposition in order to evaluate the impact of SiN deposition process itself on the device performance (denoted as the SiN-removal split). Wafers were then combined to receive a 200 nm-thick TEOS as the topmost passivation layer, followed by contact holes and metallization processes. Finally, the processing steps were completed with a forming gas anneal at 400˚C. The cross-sectional TEM pictures for SiN-capped, control, BL-10nmTEOS, BL-20nmTEOS, BL-10nmPOLY, and BL-20nmPOLY samples were shown in Fig. 2.1(a) ~ Fig. 2.1(f), respectively. Electrical characterizations were performed using an Agilent 4156 system. The interface traps were evaluated using the charge pumping method with a fixed amplitude of 1.5V at 1MHz.
2.3 Results and Discussion
2.3-1 Effects of Channel Strain on Device Performance
The stress induced by LPCVD SiN layer with and without TEOS or poly-Si buffer layer was first examined by a Tencor FLX-2320 stress measurement system. This system evaluates the stress by measuring the changes in curvature of the silicon substrate before and after deposition of a blanket SiN film with or without buffer layer.
We confirmed that the stresses are tensile in nature with a magnitude of around 300 MPa for all samples, irrespective of the presence of TEOS or poly-Si, indicating that the incorporation of either 10 nm-thick or 20 nm-thick buffer layer does not jeopardize the stress induced by SiN capping.
Next, the electrical characteristics were performed using an Agilent 4156 system.
Figure 2.2 shows the subthreshold characteristics and transconductance of NMOSFETs for all splits (i.e., control, SiN-capped, BL-10nmTEOS, BL-20nmTEOS, BL-10nmPOLY, BL-20nmPOLY, and SiN-removal) with channel length of 0.4 μm. It
can be seen that all splits exhibit similar subthreshold slope, confined in a narrow range between 74 ~ 75 mV/decade, as shown in Fig. 2.3. Nevertheless, two categories of transconductance are clearly distinguished among the samples: SiN-capped and all buffer-layer splits depict significant increase with respective to the control, while such an enhancement disappears in the SiN-removal sample. Two important implications are obtained from the results: (1). The performance enhancement is indeed related the channel strain induced by the SiN capping layer. (2). Insertion of the 10 nm-thick or 20 nm-thick TEOS or poly-Si buffer layer between the SiN and the gate does not sacrifice such performance enhancement. To validate these findings, output characteristics of NMOSFETs are shown and compared in Fig. 2.4. Still, drive current enhancement over the control sample is clearly observed for the SiN-capped and all buffer-layer splits, while SiN-removal samples show negligible enhancement.
It should be noted that such performance improvement is related to the device dimensions, a unique feature associated with the uniaxial channel strain [19-20]. To illustrate this point, Figure 2.5 shows the percentage increase of the transconductance for the SiN-capped, all buffer-layer splits, and SiN-removal samples with respect to the controls, as a function of channel length. Each datum point represents the mean measurement result performed on six devices in this figure. We can see that the transconductance enhancement reaches about 33% at a channel length of 0.4 μm in SiN-capped and all buffer-layer samples. When the SiN capping layer is removed, such enhancement becomes negligible. These observations demonstrate that the transconductance is truly due to the uniaxial tensile strain induced by the SiN capping which increases with decreasing channel length and the induced tensile strain is not released by such buffer layer. The capacitance-voltage (C-V) characteristics of the samples are shown in Fig. 2.6. Basically the C-V curves coincided altogether, indicating
that the above observations are not caused by the thickness difference among gate oxides. In addition, the physical thickness of gate oxide was also evidenced from the TEM pictures in Fig. 2.1(a) ~ Fig. 2.1(f).
2.3-2 Oxide Thickness and Barrier Height Extracted by Fowler-Nordheim Current Several techniques have been adopted to extract gate oxide thickness, such as the above-mentioned TEM image that can directly extract the physical oxide thickness or C-V measurement method to extract electrical oxide thickness. In this section, by fitting
the Fowler-Nordheim (F-N) tunneling current model to the measured data, not only the
the Fowler-Nordheim (F-N) tunneling current model to the measured data, not only the