具有氮化矽覆蓋之形變通道金氧半場效電晶體特性與相關可靠性問題研究

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(1)國立交通大學電子工程學系電子研究所博士論文. 具有氮化矽覆蓋之形變通道金氧半場效電晶體特性與相關可靠性問題研究 A Study on Characteristics and Reliability Issues of Strained Channel MOSFETs with SiN Capping. 研究生：盧景森指導教授：林鴻志博士黃調元博士. 中華民國九十七年十一月.

(2) 具有氮化矽覆蓋之形變通道金氧半場效電晶體特性與相關可靠性問題研究 A Study on Characteristics and Reliability Issues of Strained Channel MOSFETs with SiN Capping. 研究生：盧景森. Student：Ching-Sen Lu. 指導教授：林鴻志博士黃調元博士. Advisors：Dr. Horng-Chih Lin Dr. Tiao-Yuan Huang. 國立交通大學電子工程學系電子研究所博士論文. A Dissertation Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical and Computer Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering November 2008 Hsinchu, Taiwan, Republic of China. 中華民國九十七年十一月.

(3) 具有氮化矽覆蓋之形變通道金氧半場效電晶體特性與相關可靠性問題研究研究生：盧景森. 指導教授：林鴻志博士黃調元博士. 國立交通大學電子工程學系電子研究所. 摘. 要. 在本論文中，我們針對氮化矽覆蓋層對元件特性與相關可靠性影響作一系列之研究，主要涵蓋內容包括具有薄緩衝層(buffer layer)之氮化矽覆蓋 n 型與 p 型通道金氧半場效電晶體之製作與特性分析；利用改變前趨物氣體流量與沉積溫度，來最佳化氮化矽薄膜；以及對具有氮化矽覆蓋之元件作漏電流機制分析與閃爍雜訊(flicker noise)之探討。此外，我們也對氮化矽覆蓋造成的能階窄化效應(bandgap narrowing effect)與熱載子測試(hot-carrier stress)後之界面缺陷橫向分佈及負偏壓溫度不穩定性(NBTI)之交流可靠性分析做詳細的探討。我們發現，雖然氮化矽覆蓋能有效提升載子遷移率及驅動電流，但卻犧牲熱載子與負偏壓溫度不穩定之可靠性，其主要原因歸咎於沉積氮化矽的過程，使用含氫元素的反應氣體，如氨氣(NH3)、矽甲烷(SiH4)，使得大量的氫元素擴散進入通道區域，因而造成熱載子與負偏壓溫度不穩定性之劣化。為了消弭這項缺失，我們提出，利用在閘極與氮化矽覆蓋層間加入一層薄緩衝層來抑制氫的擴散，結果證實，熱載子與負偏壓溫度不穩定之可靠性均獲得顯著改善，而且不會犧牲因氮化矽覆蓋造成之元件電流提升。因為氮化矽覆蓋層中的氫是劣化元件可靠性之主因，因此，接下來我們藉由 i.

(4) 改變前趨物氣體流量與沉積溫度，直接調整氮化矽薄膜的組成。從 X 光光電子能譜術(XPS)與傅立葉轉換紅外光譜儀(FTIR)及應力量測系統之分析結果，我們發現，增加氮氣流量會增加氮化矽薄膜之伸張應力與氮含量，這是有助於 n 型通道元件之載子遷移率提升，此外，增加氮氣流量與沉積溫度會消減氮化矽中的矽氫鍵結，因此，可提升熱載子或負偏壓溫度不穩定之可靠性。接下來，雖然伸張應力能提升 n 型金氧半場效電晶體之特性，但卻造成元件關閉時漏電流增加。結果顯示，閘極引發汲極漏電(gate-induced drain leakage)為此漏電流增加之主要原因。伸張應力造成之能階窄化將增強能帶與能帶間的穿遂 (band-to-band tunneling)，因此導致閘極引發汲極漏電增加。這也說明了為何伸張應力會增加元件之漏電流。最後，我們探討氮化矽覆蓋元件對閃爍雜訊之影響。雖然在沉積氮化矽過程中增加氮氣流量能提升 n 型通道金氧半場效電晶體之特性與可靠性，但氮化矽中氫含量之減少將降低界面處缺陷與懸浮鍵(dangling bond)之修補，因為此缺陷為造成閃爍雜訊之主因，故導致閃爍雜訊劣化。. 關鍵字: 氮化矽覆蓋，緩衝層，氫擴散，氣體流量，閘極引發汲極漏電，負偏壓溫度不穩定性，熱載子測試，閃爍雜訊. ii.

(5) A Study on Characteristics and Reliability Issues of Strained Channel MOSFETs with SiN Capping Student：Ching-Sen Lu. Advisors：Dr. Horng-Chih Lin Dr. Tiao-Yuan Huang. Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University. Abstract In this thesis, we have investigated the impacts of SiN capping layer on the device performance and the related reliability issues. This study includes the fabrication and characterization of SiN-capped n- and p-channel MOSFETs with a thin buffer layer over the gate, the optimization of SiN film by varying precursor gas flow rate and deposition temperature, and investigation of off-state leakage current mechanism and flicker noise characteristics on the SiN-capped devices. In addition, bandgap narrowing effect induced by SiN capping, lateral distribution of interface state after hot-carrier stress, and AC NBTI stress are also investigated. We found that although the SiN capping can dramatically enhance the carrier mobility and thus the drive current, the robustness to hot-carrier and negative bias temperature instability (NBTI) degradation is compromised as well, owing to the large amount of hydrogen contained in the SiN layer by using the hydrogen-containing precursors, i.e., NH3 and SiH4, which may diffuse into the channel region during the SiN deposition process. To eliminate this shortcoming, the insertion of a thin buffer layer between the gate and the SiN capping layer was proposed to suppress the diffusion of hydrogen, and the result demonstrates that the hot-carrier and NBTI reliability of the SiN-capped devices can be restored without compromising the current enhancement by. iii.

(6) the SiN capping. Since abundant hydrogen species contained in the SiN capping layer are the primary culprit for aggravated reliability, we have directly adjusted the composition of SiN film by varying precursor gas flow rate and deposition temperature. From the analysis of X-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectrometer (FTIR), and stress measurement system, we found that increasing N2 flow rate will increase tensile stress and nitrogen content in the SiN film, which is beneficial for mobility enhancement of n-channel devices. In addition, increase in N2 flow rate and deposition temperature tend to weaken the signal of Si-H bonds, which is helpful for the improvement of hot-carrier and NBTI reliability. In addition, although tensile stress can boost NMOSFETs’ performance, we found that it also results in off-state leakage current increase. Our results indicate that gate-induced drain leakage (GIDL) current is the major reason for increased off-state leakage current. Bandgap narrowing induced by tensile stress will enhance the band-to-band tunneling process, resulting in GIDL current increase, which accounts for off-state leakage current increase by tensile stress. Finally, we have also investigated the impacts of SiN-capped devices on the flicker noise characteristics. Although NMOSFETs’ performance and hot-carrier reliability can be improved by increasing N2 flow rate in the SiN deposition, the accompanying decrease of hydrogen content reduces the passivation of defects and dangling bonds near the interface, which is considered to be the main culprit for flicker noise, resulting in the degradation of flicker noise.. Keyword: SiN capping, buffer layer, hydrogen diffusion, gas flow rate, gate-induced drain leakage (GIDL), negative bias temperature instability (NBTI), hot-carrier stress, flicker noise. iv.

(7) 誌. 謝. 本論文的完成，首先，要特別感謝我的指導教授林鴻志博士與黃調元博士。林老師提供了我很多學習的機會，讓我在求學期間，就曾在台積電與工研院打工，提早跟業界接觸與學習，也提供了我很多實驗上的想法，讓我燃起鬥志重新回學校做實驗，而老師對元件物理的觀念以及研究嚴謹的態度，更讓學生獲益良多，雖然老師常常說自己很嘮叨，但是學生還是非常感激老師的用心與指教；黃老師博學多聞，做事小心謹慎，且待人和藹可親彬彬有禮，不僅學術上的專業，平常處世的方法與態度以及文學上的造詣，都讓學生非常佩服。有幸獲得兩位恩師的教導，學生感激之情，實難以用言語形容。另外要感謝簡昭欣老師與郭治群老師，謝謝你們平日對學生的關心與祝福。由衷感謝呂嘉裕學長帶我進入無塵室，給予我啟蒙訓練以及實驗上的傳承；感謝李耀仁學長在我徬徨時給予鼓勵並提供建議與幫忙；感謝侯拓宏、歐士傑、吳偉豪、林宏年、俞正明、李達元與陳啟群等學長在台積電的照顧；感謝陳百宏、林哲歆學長在工研院的幫助；感謝葉冠麟、李明賢、盧文泰、李維、賴大偉等學長在實驗上的建議與分享；感謝與我同屆的蘇俊榮在研究路上的陪伴；感謝與我一起打拚的黃健銘、陳瀅弘、蔡子儀、詹凱翔等學弟，讓我不再孤軍奮戰，以及先進元件技術實驗室的學弟，張伊鋒、張凱翔、徐行徽、謝雨霖、趙志誠、陳威臣、李冠樟、林哲民、林政頤、郭嘉豪及其他碩班的學弟妹們，在這段期間的陪伴與相互鼓勵學習；也感謝我曾經帶過的專題生，陳宇航與邱筱芸在研究上的幫忙。另外，衷心的感謝國家奈米元件實驗室，提供良好的設備與環境，並感謝沈士文、謝錦龍、彭馨誼、劉正財、宋金龍、范庭瑋、李春杏、陳琇芝、周家如、徐台鳳、林婉貞、蔣秋芬、趙子綾、魏雅嵐、蕭明娟等人在元件製作上的協助；感謝陳坤明博士與陳柏源先生在高頻實驗室裡的幫忙；以及感謝那些許許多多曾經幫助過我的人。特別要感謝我的父母，盧振興先生與林月祝女士，感謝你們三十年來的養育之恩，並總是默默的在背後給予我支持與協助；感謝我的妹妹盧佩宜小姐以及所有關心我的親朋好友，在我求學時間的支持與鼓勵；再則更要感謝我女友王品雯小姐，在研究路上有你的關心與陪伴，讓我不再孤單。你們的關心，是我精神的慰藉，也提供了我繼續向前的動力。最後，謹以此論文獻給我的家人，及所有關心我的朋友。盧景森誌于風城交大 2008/11 v.

(8) Contents Abstract (Chinese)……………………………………………………………………... i. Abstract (English)…………………………………………………………………….... iii. Acknowledgement (Chinese)…………………………………………………………... v. Contents ………………………………………………………………………………... vi. Table Captions …………………………………………………………………………. x. Figure Captions ………………………………………………………………………... xi. Chapter 1 Introduction………………………………………………………………... 1 1.1 General Background……………………………………………………………… 1 1.1-1 Strained Channel Technology……………………………………………... 1. 1.1-2 Mobility Enhancement Physics………………………………………….... 2. 1.1-3 Hot-Carrier Effects………………………………………………………... 4. 1.1-4 Negative Bias Temperature Instability (NBTI)…………………………… 5 1.1-5 Flicker Noise Characteristics…………………………………………….... 6. 1.2 Motivation……………………………………………………………………….... 8. 1.3 Thesis Organization ……………………………………………………………… 9 References ……………………………………………………………………………. 12. Chapter 2 Impacts of Buffer Layer on the Performance and Reliability of Strained Channel NMOSFETs with SiN Capping……………………….. 21. 2.1 Introduction ………………………………………………………………………. 21. 2.2 Devices Fabrication ……………………………………………………………… 22 2.3 Results and Discussion …………………………………………………………... 23 vi.

(9) 2.3-1 Effects of Channel Strain on Device Performance ……………………….. 23. 2.3-2 Oxide Thickness and Barrier Height Extracted by Fowler-Nordheim Current ……………………………………………………………………. 25 2.3-3 Short Channel Effects …………………………………………………….. 27. 2.3-4 Hot-Carrier Stress ……………………………………………………….... 28. 2.3-5 Lateral Distribution of Interface State ……………………………………. 31. 2.3-6 Optimization of Buffer Layer Thickness …………………………………. 33. 2.4 Summary ………………………………………………………………………. 34. References …………………………………………………………………………. 36. Chapter 3 Optimization of SiN Deposition Conditions and Its Impacts on Strained n- and p-Channel MOSFETs……………………………………. 80. 3.1 Introduction ………………………………………………………………………. 80. 3.2 Devices Fabrication ……………………………………………………………… 81 3.3 Results and Discussion …………………………………………………………... 82 3.3-1 Material Analysis …………………………………………………………. 82. 3.3-2 Devices Characteristics for NMOSFETs …………………………………. 83. 3.3-3 Hot-Carrier Stress for NMOSFETs ………………………………………. 84. 3.3-4 Impacts of Performance and NBTI Reliability on PMOSFETs ………….. 86. 3.4 Summary …………………………………………………………………………. 88. References ……………………………………………………………………………. 89. Chapter 4 Off-State Leakage Current Mechanisms of Strained Channel NMOSFTs with Different SiN Thickness and Its Impacts on the Performance and Hot-Carrier Reliability………………………………... vii. 116.

(10) 4.1 Introduction ………………………………………………………………………. 116. 4.2 Devices Fabrication ……………………………………………………………… 117 4.3 Results and Discussion …………………………………………………………... 118 4.3-1 Device Characteristics ……………………………………………………. 118. 4.3-2 Off-State Leakage Current ………………………………………………... 119. 4.3-3 Hot-Carrier Stress ……………………………………………………….... 120. 4.4 Summary …………………………………………………………………………. 122. References ……………………………………………………………………………. 123. Chapter 5 Improvements of Negative-Bias-Temperature Instability in SiN-Capped p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Using Ultra-thin HfO2 Buffer Layer……………………….... 147. 5.1 Introduction ………………………………………………………………………. 147. 5.2 Devices Fabrication ……………………………………………………………… 148 5.3 Results and Discussion …………………………………………………………... 149 5.3-1 Devices Characteristics …………………………………………………... 149 5.3-2 Negative Bias Temperature Instability Characterization …………………. 150. 5.4 Summary …………………………………………………………………………. 153. References ……………………………………………………………………………. 154. Chapter 6 Impacts of SiN-Capped NMOSFETs on the Flicker Noise Characteristics……………………………………………………………... 174 6.1 Introduction ………………………………………………………………………. 174. 6.2 Devices Fabrication ……………………………………………………………… 175 6.3 Flicker Noise Measurement Setup ……………………………………………….. viii. 175.

(11) 6.4 Results and Discussion …………………………………………………………... 176 6.4-1 SiN Film Analysis ………………………………………………………... 176 6.4-2 Basic Electrical Characteristics………………………………………….... 176. 6.4-3 Flicker Noise Characteristics…………………………………………….... 177. 6.5 Summary …………………………………………………………………………. 179. References ……………………………………………………………………………. 180. Chapter 7 Conclusions and Suggested Future Works……………………………….. 198. 7.1 Conclusions ………………………………………………………………………. 198. 7.2 Suggestions for Future Work …………………………………………………….. 201. Vita (Chinese)…………………………………………………………………………... 203. Publication list………………………………………………………………………….. 204. ix.

(12) Table Captions Chapter 1 Table 1-I Impacts of 3D strain direction on device performance. X represents the longitudinal direction of carrier transport, Y represents the in-plane transverse direction of carrier transport, and Z represents the direction of out-of-plane. .…………………………………………………………….20. Chapter 3 Table 3-I Precursor flow rates, deposition temperature, and measured tensile stress for SiN film. Deposition pressure and rf power were fixed at 1 Torr and 100W, respectively. ……………………………………………………...95. Chapter 4 Table 4-I Split conditions for all samples, denoted as control, SiN-200Å, and SiN-1000Å, respectively. ……………………………………………....128. Chapter 6 Table 6-I Precursor flow and SiN film properties. 1Determined form the XPS results; 2 from the FTIR results. …………………………………………………184. x.

(13) Figure Captions Chapter 2 Fig. 2.1. Cross-sectional TEM pictures for (a) SiN-capped, (b) control, (c) BL-10nmTEOS,. (d). BL-20nmTEOS,. (e). BL-10nmPOLY,. (f). BL-20nmPOLY samples. ………………………………………………….42 Fig. 2.2. Subthreshold characteristics and transconductance for all seven splits of NMOSFETs. The subthreshold swing is nearly identical among the seven splits, while the transconductance is obviously larger for the SiN-capped and all buffer-layer samples. …………………………………………………...48. Fig. 2.3. Subthreshold swing of NMOSFETs for all splits of samples with W/L = 10/0.4 μm. ………………………………………………………………….49. Fig. 2.4. Output characteristics of NMOSFETs for all splits. Drive current enhancement is clearly observed for the SiN-capped and all buffer-layer splits. The SiN-removal sample shows negligible enhancement. ………….50. Fig. 2.5. Percentage increase of transconductance versus channel length for all splits of samples with respect to the control ones. Each datum point represents the mean measurement result performed on six devices. ……………………...51. Fig. 2.6. Capacitance-Voltage (C-V) characteristics for all seven splits. Basically the seven splits show almost identical curves, indicating that the oxide thickness difference among these seven splits is negligible. …………………………52. Fig. 2.7. Energy band diagram illustrating F-N tunneling. ………………………….53. Fig. 2.8. The plot of JG versus VG for control samples. The extracted oxide thickness by F-N current fitting is about 2.919 nm. ………………………………….54. Fig. 2.9. F-N plot for control samples. The extracted barrier height is about 3.03 eV. ………………………………………………………………………….55. xi.

(14) Fig. 2.10 The plot of JG versus VG for all splits. …………………………………….56 Fig. 2.11 The extracted barrier height versus gate oxide thickness for all splits. We can see that the barrier heights for all SiN capping samples are larger than control ones. ………………………………………………………………..57 Fig. 2.12 The extracted barrier height for thicker gate oxide thickness (around ~4.3 nm). The barrier height for non-strained samples is close to 3.1 eV, while the SiN capping samples still exhibit barrier height increased of about 100 meV. ………………………………………………………………………..58 Fig. 2.13 Threshold voltage roll-off characteristics as a function of channel length for all splits of samples. ………………………………………………………..59 Fig. 2.14 Drain induced barrier lowering (DIBL) characteristics as a function of channel length for all splits of samples. …………………………………...60 Fig. 2.15 Substrate current versus gate voltage for all splits of samples with W/L = 10/0.5 μm. ………………………………………………………………….61 Fig. 2.16 Subthreshold characteristics and tranconductance of devices with W/L = 10/0.5 μm before and after 5000 sec hot-carrier stressing for (a) control, (b) SiN-capped, (c) BL-10nmTEOS, (d) BL-20nmTEOS, (e) BL-10nmPOLY, (f) BL-20nmPOLY, and (f) SiN-removal samples. ……………………………62 Fig. 2.17 Threshold voltage shift as a function of stress time. Devices with W/L = 10/0.5 μm were stressed at VDS = 4.9 V, and VG of maximum substrate current. Each datum point represents the mean measurement results performed on three devices. ………………………………………………..69 Fig. 2.18 (a) In SiN-capping devices, a large amount of hydrogen species from the SiN layer diffuse to the gate oxide layer and the channel region through three possible pathways. (b) In the devices with buffer layer, the diffusion of. xii.

(15) hydrogen species can be suppressed by the buffer layer. ………………….70 Fig. 2.19 Charge pumping current for all SiN-capping samples, with or without buffer layer. W/L = 10/0.5 μm. ……………………………………………………71 Fig. 2.20 Single junction charge pumping measurement setup. …………..................72 Fig. 2.21 Nonuniform distribution of local threshold voltage and flatband voltages across the device caused by variation in lateral doping concentration. ……73 Fig. 2.22 Derived relationship between local threshold voltage and lateral distance x from single junction charge pumping data of the control device. …………74 Fig. 2.23 Extracted lateral profile of local threshold voltage near graded drain junction in the control sample. ……………………………………………………....75 Fig. 2.24 Charge pumping current before and after 100 s hot-carrier stressing (VG at Isub,max and VDS = 4.9 V) with W/L = 10/0.5 μm. ………………..................76 Fig. 2.25 Lateral profile of interface state generation after hot-carrier stress for all splits of samples. …………………………………………………...............77 Fig. 2.26 Subthreshold characteristics and transconductance of NMOSFETs for control, SiN-capped, BL-10nmTEOS, BL-30nmTEOS, and BL-50nmTEOS splits.. The. transconductance. enhancement. starts. to. diminish. for. BL-30nmTEOS split. ………………………………………………............78 Fig. 2.27 Threshold voltage shift as a function of stress time. Devices with W/L = 10/0.5 μm were stressed at VDS = 4.6 V, and VG of maximum substrate current. ……………………………………………………………………..79. Chapter 3 Fig. 3.1. Schematic structure of fabricated devices with different types of passivation. The passivation thickness is fixed at 300 nm. ……………………………..94. xiii.

(16) Fig. 3.2. (a) Results of XPS analysis for SiN-1, SiN-2, and SiN-3 splits. The SiN-3 split contains the highest N content among all splits, owing to the use of the highest N2 flow rate in the deposition process. (b) Results of XPS analysis for SiN-1(400°C), and SiN-3(400°C) splits. The SiN-1(400°C) and SiN-3(400°C) samples depict similar trend with the SiN-1 and SiN-3 split, respectively, implying that N content in the SiN film does not seem to be affected by the temperature of 400°C. ……………………………………..96. Fig. 3.3. Results of FTIR analysis: SiN-1 sample contains the highest number of Si-H bonds among all splits. Increase in N2 flow rate and deposition temperature tends to weaken the signal of Si-H bonds. …………………………………98. Fig. 3.4. Tensile stress versus N2 flow rate. The tensile stress increases with increasing N2 flow rate. ……………………………………………………99. Fig. 3.5. Transconductance (Gm) versus VG-Vth for all splits with W/L = 10/0.4 μm. The SiN-3 and SiN-3(400°C) splits depict the largest and identical Gm among all splits, owing to the largest tensile stress level. ………………..100. Fig. 3.6. Output characteristics of NMOSFETs for all splits. The enhancement trend in drive current is similar to that of Gm enhancement. …………..............101. Fig. 3.7. Gmmax as a function of tensile stress with W/L = 10/0.4 μm for all SiN-capped splits. Gmmax increases with increasing tensile stress and a linear dependence is observed in the figure. …………………………………….102. Fig. 3.8. The percentage increase of Gm for all SiN-capping samples, compared with the SiO2 controls, as a function of channel length. Each datum point represents the mean measurement result performed on six devices. ……..103. Fig. 3.9. Capacitance-Voltage (C-V) characteristics for all splits of samples. The C-V curves coincide altogether, indicating that the above-mentioned results are. xiv.

(17) not caused by oxide thickness difference. ……………………………….104 Fig. 3.10 Subthreshold characteristics of NMOSFETs for all splits with W/L = 10/0.4 μm. ……………………………………………………………………….105 Fig. 3.11 Subthreshold swing of NMOSFETs for all splits with W/L = 10/0.4 μm...106 Fig. 3.12 Threshold voltage shift (ΔVth) as a function of stress time for all splits. Devices were stressed at VDS = 4.6 V, and VG at maximum substrate current. ΔVth is defined as Vth(t) – Vth(0) for transistors with W/L = 10/0.5 μm. ...107 Fig. 3.13 The difference of charge pumping current before and after 1000 sec hot-carrier stress among all splits. The largest amount of interface states are generated for SiN-1 split, while SiN-3(400°C) split fares better in this aspect. …………………………………………………………………….108 Fig. 3.14 Charge pumping current before and after 200 s hot-carrier stress for a control sample. ……………………………………………………………………109 Fig. 3.15 Lateral distribution of interface state generation after hot-carrier stress for all splits. The major damage region is confined within 0.1 μm near the drain edge. ………………………………………………………………………110 Fig. 3.16 Transconductance versus VG-Vth for the three SiN-capped PMOSFET splits. Transconductance is degraded by SiN-1 and SiN-3 capping layers, especially for SiN-3 capping samples, since SiN-3 film depicts maximum tensile stress. ………………………………………………………………..........111 Fig. 3.17 Maximum filed-effect mobility of PMOSFETs for SiN-1, SiN-3, and the control. Each datum point represents the mean measurement results performed on four devices. ……………………………………………….112 Fig. 3.18 Capacitance-Voltage (C-V) characteristics for SiN-1, SiN-3, and the control. These C-V curves also coincide altogether, indicating the performance. xv.

(18) degradation is not caused by the oxide thickness difference. …………….113 Fig. 3.19 The setup of NBTI measurement with source, drain and substrate grounded and gate bias of VG-Vth = -3.3 V at temperature of 125°C. ………………114 Fig. 3.20 Threshold voltage shift (ΔVth) of PMOSFETs versus stress time for SiN-1, SiN-3, and the control. The NBTI stress was performed with VG-Vth = -3.3 V at temperature of 125°C. The p_SiN-1 split depicts the worst NBTI degradation in terms of the largest threshold voltage shift, while the NBTI degradation in p_SiN-3 split is mitigated and becomes comparable to that of the SiO2 control. ………………………………………………………......115. Chapter 4 Fig. 4.1. The schematic structure of fabricated devices with different types of passivation. The total passivation thickness, including SiN and SiO2, is fixed at 3000 Å. ………………………………………………………………...127. Fig. 4.2. Transconductance (Gm) enhancement with W/L = 10/0.6 μm for all splits of samples. Gm increases with increasing SiN thickness, confirming that the stress becomes more tensile as the SiN thickness increases. ……………..129. Fig. 4.3. Capacitance-Voltage (C-V) characteristics for all splits of samples, showing almost identical curves and the extracted electrical thickness is about 3.38 nm. ………………………………………………………………………..130. Fig. 4.4. Subthreshold characteristics of NMOSFETs for all splits of samples with W/L = 10/0.6 μm. The SiN-1000Å split depicts the largest off-state leakage current among all splits and the leakage current increases with increasing gate bias. ……………………………………………………………….....131. Fig. 4.5. Extracted subthreshold swings for all splits. They are confined in a narrow. xvi.

(19) range between 76 ~ 77 mV/decade. ……………………………………...132 Fig. 4.6. Threshold voltage (Vth) roll-off characteristics for all splits of devices. ...133. Fig. 4.7. Illustration of various leakage paths for NMOSFETs with Vd = 1.5 V, Vg = 0 ~ -1 V, and Vs = Vb = 0 V. ……………………………………………….134. Fig. 4.8. The four-terminal leakage current (Id_off, Ig_off, Is_off, and Ib_off) for (a) control, and (b) SiN-1000Å samples, respectively, when Vg was swept from 0 to -1 V and Vd fixed at 1.5 V. …………………………………………..135. Fig. 4.9. Substrate currents for all splits of samples, showing that SiN-1000Å split depicts the largest Ib_off current among all splits. ……………………….136. Fig. 4.10 Statistical box plot of off-state current for all splits. These data were measured from seven different die positions with Vd = 1.5 V and Vg = -0.9 V at W/L = 10/0.6 μm. ……………………………………………………137 Fig. 4.11 Schematic energy band diagram of the gate-drain overlap region. ………138 Fig. 4.12 Substrate current (Isub) versus gate voltage for all splits of devices with W/L = 10/0.5 μm at VDS = 4.5 V. Substrate current increases with increasing SiN thickness. …………………………………………………………………139 Fig. 4.13 Subthreshold characteristics and transconductance before and after 5000 sec hot-carrier stress for (a) control, (b) SiN-200Å, and (c) SiN-1000Å samples. …………………………………………………………………..140 Fig. 4.14 Threshold voltage shift as a function of stress time. Devices with W/L = 10/0.5 μm were stressed at VDS = 4.5 V, and VG of maximum substrate current. ……………………………………………………………………143 Fig. 4.15 Bonding signals of PECVD SiN film measured by Fourier transform infrared spectrometer (FTIR). Extra Si-H bonding signals are observed, implying that SiN film indeed has higher hydrogen content. ……………………...........144. xvii.

(20) Fig. 4.16 The difference of charge pumping current before and after 5000 sec hot-carrier stress for all splits of samples. More interface states are generated during the hot-carrier stress for SiN-1000Å split. ………………………..145 Fig. 4.17 Lateral profile of interface state generation after hot-carrier stress for all splits of devices. Hot-carrier degradation is highly localized and the major damage region is confined within 0.1 μm near the drain edge. …………..146. Chapter 5 Fig. 5.1. Cross-sectional TEM pictures of HfO2-buffered samples taken in (a) passivation region and (b) spacer region. The thickness of SiN and HfO2 buffer layer is roughly 310 nm and 3 nm, respectively. ………………….157. Fig. 5.2. Setups of (a) charge pumping measurement, (b) DC NBTI stress measurement, and (c) AC NBTI stress measurement. ……………………159. Fig. 5.3. Transconductance versus VG-Vth for all splits of samples. For the SiN-capped devices, with or without inserting the buffer layer, the transconductance is clearly increased with respective to the control. ……161. Fig. 5.4. Output characteristics of PMOSFETs for all splits. The insertion of the HfO2 buffer in the SiN-capped device does not compromise the drive current enhancement with respective to the control. ……………………………..162. Fig. 5.5. Transconductance increase versus channel length. Each datum point represents the mean measurement result performed on eight devices. …..163. Fig. 5.6. Capacitance-Voltage (C-V) characteristics of all splits. The curves are almost coincided with each other, indicating that the oxide thickness difference among the three splits is negligible. ……………………………………...164. Fig. 5.7. Subthreshold characteristics of all splits. …………………………….......165. xviii.

(21) Fig. 5.8. Subthreshold swing of all splits. We can see that the subthreshold characteristics are not affected by the presence of SiN and HfO2-buffer layers. ……………………………………………………………………..166. Fig. 5.9. Threshold voltage shift (ΔVth) versus stress time for HfO2-buffered split under three different gate biases at 125°C. ……………………………….167. Fig. 5.10 Threshold voltage shift (ΔVth) versus stress time for all three splits with VG-Vth = -3.5 V at 125°C. It is seen that the SiN-capped split depicts much larger ΔVth as compared with the control split. Such degradation is partially relieved when the HfO2 buffer layer is added. ……………………….......168 Fig. 5.11 Interface state generation (ΔNit) and subthreshold swing degradation (ΔSwing) versus stress time for all three splits with VG-Vth = -3.5 V at 125°C. …………………………………………………………………….169 Fig. 5.12 Transconductance degradation versus stress time for all three splits with VG-Vth = -3.5V at 125°C. The transconductance degradation ratio for SiN-capped split depicts the severest degradation among all three splits, while this degradation is alleviated for HfO2-buffered split. ……………..170 Fig. 5.13 Bonding signals of PECVD-SiN layer by Fourier transform infrared spectrometer (FTIR). Visible H-bonding signals can be detected, indicating that the SiN film indeed contains a substantial amount of hydrogen. ……171 Fig. 5.14 Threshold voltage shift of devices with thin HfO2 buffer layer, measured at different AC stress frequencies with VG-Vth = -3.5 V at 125°C. It can be seen that Vth depicts less shift at higher frequency. ……………………….......172 Fig. 5.15 Threshold voltage shift as a function of frequency for devices with different split conditions after VG-Vth = -3.5 V, 1000s stress at 125°C. ……………173. xix.

(22) Chapter 6 Fig. 6.1. Schematic structure of the fabricated device with different types of passivation. The thickness is fixed at 300 nm. ……………………….......183. Fig. 6.2. Schematic setup for flicker noise measurement. …………………………185. Fig. 6.3. Results of XPS analysis, indicating that the SiN-3 split contains the highest N content among all splits, owing to the use of the highest N2 flow rate in the deposition process. ………………………………………………………..186. Fig. 6.4. Results of FTIR analysis, indicating that the SiN-1 split contains the highest number of Si-H bonds among all splits. Increase in N2 flow rate tends to weaken the signal of Si-H bonds. …………………………………...........187. Fig. 6.5. Subthreshold characteristics and transconductance (Gm) of the fabricated NMOSFETs for all splits. …………………………………………...........188. Fig. 6.6. Output characteristics of NMOSFETs for all splits. ……………………...189. Fig. 6.7. Drain current noise spectral density (SId) for all splits with W/L = 10/0.6 μm under Vg = 1.5 V and Vd = 0.05 V. ………………………………………190. Fig. 6.8. Input-referred gate voltage noise spectral density (SVg) for all splits with W/L = 10/0.6 μm under Vg = 1.5 V and Vd = 0.05 V. ……………...........191. Fig. 6.9. SVg@25 Hz for all splits under Vg = 0.5 V and Vd = 0.05V. Each datum point represents the mean measurement result from five devices. ……….192. Fig. 6.10 Extracted oxide trap density (Not) for all splits. Each datum point represents the mean measurement result from five devices. …………………….......193 Fig. 6.11 Charge pumping current for SiN splits with pulse amplitude of 1.5 V and f = 1 MHz. ……………………………………………………………………194 Fig. 6.12 Extracted interface state (Nit) from the charge pumping current. The SiN-1 split still depicts the minimum Nit. ………………………………….........195. xx.

(23) Fig. 6.13 Input-referred gate voltage noise spectral density (SVg) as a function of gate voltage at Vd = 0.05 V and f = 25 Hz. ……………………………………196 Fig. 6.14 Extracted oxide trap density (Not) as a function of gate voltage at Vd = 0.05 V and f = 25 Hz. ……………………………………………………….....197. xxi.

(24) Chapter 1 Introduction 1.1 General Background 1.1-1 Strained Channel Technology The origin of strained channel to improve MOS devices can be traced back to thin Si layers grown on relaxed SiGe substrates in the 1980s [1-2]. The thin Si layer takes the larger lattice constant of the SiGe and creates bi-axial tensile stress. Drive current of both NMOSFET and PMOSFET can be enhanced by the bi-axial tensile stress when more than 20% of Ge is incorporated in the relaxed SiGe layer [3]. It is noted that the thickness of the top strained-Si layer must be thinner than a critical thickness that depends on the Ge content of the underlying relaxed SiGe layer to avoid the generation of high amount of dislocations. The yield issue associated with high threading dislocation density (typically > 104 cm-2) of the virtual SiGe substrate represents a major obstacle for practical applications. In addition to defect issue, bi-axial strain suffers from other concerns such as high Ge out-diffusion, high wafer cost, and performance loss at high vertical electric field [4]. In the 1990s, another strained channel technology was proposed, i.e., so-called uni-axial strain, which is based on process-induced strain and free from the aforementioned concerns of bi-axial strain. Uni-axial strain was experimentally and theoretically studied by a large number of researchers in recent years. Various methods of uni-axail strain were proposed such as using SiN contact etch-stop layer [5-8], shallow trench isolation [9-11], source/drain (S/D) silicidation [12], and embedded SiGe [13-14] or SiC [15-16] in the S/D. In addition, depending on the SiN deposition conditions, the SiN layer can generate either tensile or compressive stress [5], enabling the dual-SiN stressor technology for CMOS. 1.

(25) manufacturing [17]. Furthermore, the behaviors of carrier mobility under uni-axial strain depend on the strength of the strain and the orientation [17]. Electron and hole mobilities respond to the three-dimensional (3D) mechanical stress in different, even opposite ways. Table 1-I summarizes the impact of 3D strain direction on device performance [18]. Only increasing tensile stress in the in-plane transverse direction of carrier transport (i.e., y-direction) benefits NMOSFET’s and PMOSFET’s performance simultaneously, while it is a trade-off for stress in the other two directions. We summarize some major advantages of uni-axial versus bi-axial strain as follows. First, uni-axial stress provides significantly larger hole mobility enhancement at both low strain and high vertical electric field due to the difference in the warping of the valence band under strain [19]. Large mobility enhancement at low strain is important since yield loss via dislocations occurs at high strain. Second, uni-axial stress provides larger current improvement for nano-scale short-channel devices, and it can be enhanced by shortening the channel length [20-21]. Third, it is reported that the threshold voltage shift for devices with uni-axial stress is smaller than that with bi-axial stress [22-23]. Lastly, uni-axial stress is more easily implemented in modern VLSI technology. With these advantages, process-induced uni-axial stress is present in nearly all high performance logic technologies at the 90, 65, and 45 nm technology nodes for both microprocessor and consumer products [24-25].. 1.1-2 Mobility Enhancement Physics The carrier mobility is given by μ =. qτ , where 1/τ is the scattering rate and m* is * m. the conductivity effective mass. Strain enhances the mobility by reducing the conductivity effective mass and/or the scattering rate [26]. For electron transports in bulk Si, the conduction band is comprised of six degenerate valleys (Δ6) of the same 2.

(26) energy. Strain removes the degeneracy between the four in-plane valleys (Δ4) and the two out-of-plane valleys (Δ2) by splitting them in energy [27]. Among Δ4 valleys, two are in-plane transverse (y) and two are longitudinal (x) in the direction of carrier transport. The energy difference (ΔE) between Δ2 and Δ4 sub-bands determines the total population of the bands. The mobility enhancement will be reinforced by decreasing inter-valley scattering that results from the splitting of conduction band [28]. In addition, the lower energy of the Δ2 valleys indicates that they are preferentially occupied by electrons. The electron mobility is also improved by reducing in-plane and increasing out-of-plane effective mass due to the favorable mass of the Δ2 valleys [29]. When operating the device in strong inversion, the electrons in the inversion layer will be subjected to a strong quantum confinement [30]. Note that the Δ2 valleys are longitudinal in the direction of quantization (z) and will thus merely react. However, the Δ4 valleys are all transverse in the direction of quantization. Therefore, they will strongly increase their energy and lose their electron to Δ2 valleys [30]. The fraction of transverse electrons will further increase as will the sub-band splitting. Both will contribute to the increase of mobility in the strong inversion regime [23]. For holes, the valence band structure of Si is more complex than the conduction band [23]. Holes occupy the top two bands (i.e., heavy-hole and light-hole bands) for unstrained Si. With the application of strain, the effective mass of hole becomes highly anisotropic due to band warping, and the energy levels become mixtures of the pure heavy-hole, light-hole, and split-off bands. Thus, the light-hole and heavy-hole bands lose their meaning [31]. The light-hole band will lower the energy under the impact of strain. The fraction of light holes will increase, and that of heavy holes will decrease, leading to a lower conductivity mass, and thus a higher mobility [30]. In addition, the sub-band splitting will prevent inter-band passages of holes, and leading to a further 3.

(27) increase in mobility due to decrease in scattering rate. However, for bi-axial tensile strain in the strong inversion, the splitting of sub-bands will be cancelled [25,30]. Because under the effect of quantum confinement, the light-hole band will increase its energy much than the heavy-hole band [23]. Therefore, the initial reparation between the light and heavy holes is then restored in the hole population, and the impact on hole mobility enhancement vanishes [4].. 1.1-3 Hot-Carrier Effects One of the serious reliability problems by continued shrinking of MOSFETs into the submicron regime is the hot-carrier effect [32-34]. Hot electrons produced by the high lateral electric field near the drain in short-channel devices can generate electron-hole pairs via impact ionization, and creates more hot carriers. The resulting hot carriers are injected into the gate oxide via hot-carrier injection (HCI), leading to the creation of interface states [35]. The interface states cause threshold voltage shift and increase subthreshold slope, and degrade the device over time. One method to determine hot-carrier degradation in n-channel devices is to bias the device at maximum substrate current (Isub,max). The generated hot holes enter the substrate and constitute a parasitic substrate current, and thus substrate current can be used to indirectly monitor hot-carrier effect. The substrate current depends on the channel lateral electric field. At low gate voltage (Vg), the lateral electric field increases with increasing gate voltage until Vg = Vd/3 ~ Vd/2 [36]. Substrate current increases to a maximum at that gate voltage. For higher gate voltage, the lateral electric field decreases as does the substrate current. The device is biased at Isub,max for a certain time and the device parameters, such as threshold voltage, saturation current, transconductance, or interface states, are measured. In general, the device lifetime is. 4.

(28) defined as the time when the measured parameter has changed by 10 ~ 20%. When considering high mobility strained channel devices, it is clear that higher mobility could lead to more energetic electrons. Also, the lower bandgap in the strained-Si could make impact ionization easier [37-39]. These two factors will cause increased hot-carrier injection in the strained channel devices.. 1.1-4 Negative Bias Temperature Instability (NBTI) Negative bias temperature instability (NBTI), known since the late 1960s [40-43], has been recognized as one of the most serious reliability concerns for p-channel MOSFETs, because it can result in the failure of the integrated circuit (IC). Either negative gate voltages or an elevated temperature can produce NBTI, but a stronger and faster effect is produced by their combination. Generally, the NBTI stress is performed at an elevated temperature with oxide electric field typically below 6 MV/cm, and this leads to the degradation of device parameters, such as threshold voltage, drive current, and interface states. The degradation phenomenon of NBTI was first reported by Miura and Matukura [41], and further characterized by researchers at Bell Laboratories [43-44], Fairchild Semiconductor [40], and RCA Laboratories [42]. Despite many research efforts, detailed NBTI degradation mechanism has not yet been fully understood. NBTI depicts a fractional power-law dependence on time. The value of the exponent is most likely 1/4. From the t1/4-like evolution, Jeppson and Svensson first proposed the diffusion-controlled electrochemical reaction model for the NBTI of MOSFETs [45]. Later, this model was refined by Ogawa et al. [46-47]. The reaction can be expressed as follows, (Si/SiO2 interface defect) ↔ (fixed oxide charge)+ + (interface state) + Xinterface. 5.

(29) + e- (to the silicon) and. Xinterface ↔ Xbulk. (1-1) (1-2). where X denotes the diffusion species, which is thought to be the dissociated hydrogen species (either H0 or H+) or water-related species [45,48-49]. The initial Si/SiO2 interface defect is comprised of hydrogen-terminated trivalent Si bonds (Si-H), and interface state is supposed to be a silicon dangling bond denoted as Si‧ which results when H is removed from Si-H. When the Si/SiO2 interface defect is electrically activated, the diffusion species leaves a defect site at Si/SiO2 interface where an interface state and a positive fixed oxide charge are generated. This model agrees with the observation that equal numbers of interface states and fixed oxide charges are produced [50]. The Si-H bonds have been proposed as the origin for both fixed oxide charge and interface state generation under NBTI stress. As proven by Jeppson and Svensson [45], the behavior of the interface state generation suggests that the generation process is diffusion-controlled. Nit buildup equals the total number of released H species. Hole-assisted reaction breaks interfacial Si-H bonds, resulting in Nit generation: ΔNit = SN (Dxt)n. (1-3). where Dx is the diffusion coefficient of X in the oxide, time exponent value depends on the type of H species trapped and released in the oxide bulk [51].. 1.1-5 Flicker Noise Characteristics Flicker noise in MOSFETs has been extensively studies in the past [52-62]. It is commonly known as 1/f noise since the noise spectral density is inversely proportional to frequency. In the early days of flicker noise research in MOS devices, two major theories have been raised to explain its physical origins. 6.

(30) In the carrier number fluctuation theory, originally proposed by McWhorter [52-53], the flicker noise is attributed to the random trapping and detrapping processes of charges in the oxide traps near the Si/SiO2 interface [54-55]. Using this theory, the input-referred noise will be independent of the gate bias voltage, and the magnitude of the noise spectra is proportional to the density of the interface trap density. The slope η of the 1/fη noise spectra is usually chosen to be 1 if the trap density is assumed to be uniform in the gate oxide [56]. Based on this theory, input-referred gate voltage noise spectral density (SVg) can be given by S Id kTq 2 N ot 1 SVg = 2 = g m γ Cox2 WL f. (1-3). where SId is drain current noise spectral density; gm is transconductane; Cox is the oxide capacitance per unit area; γ is the McWhorter tunneling parameter; Not is the oxide trap density per unit volume and unit energy; W and L are channel width and length, respectively. The mobility fluctuation theory, on the other hand, considers flicker noise as a result of fluctuation in bulk mobility. This theory is based on Hooge’s empirical relation for the spectral density of flicker noise in a homogeneous sample [57]. Adapting Hooge’s model to a typical MOS device, SVg in strong inversion is given by [58]. SVg =. qα (Vg − Vth ) CoxWLf. (1-4). where α is the Coulomb scattering coefficient. This model suggests a linear dependence of SVg with the gate voltage in strong inversion. Some authors have combined both the carrier number fluctuation and the mobility fluctuation models to explain a broader set of data [59-60]. However, they have combined the two theories in an uncorrelated manner, whereas in fact both fluctuations arise from the same mechanism. Based on the new information obtained from the study 7.

(31) of random telegraph signal in small area MOSFETs, a unified flicker noise model was proposed by K. K. Hung [61-62], which incorporates both the carrier number fluctuation and the mobility fluctuation mechanisms in a correlated manner. The SVg can be written as SVg =. kTq 2 N ot (1 + αμ0Cox (Vg − Vth )) 2 γ fWLCox2. (1-5). This equation depicts that SVg will show a quadratic increase with the gate voltage.. 1.2 Motivation Channel strain engineering has been pursued aggressively for mobility enhancement in nano-scale MOS devices, especially by using uni-axial strain technology, which can be free from the concerns related to bi-axial strain arising from the use of SiGe virtual substrate, such as substrate defects, high Ge out-diffusion, self-heating, and high wafer cost. Generally, uni-axial strain can be engineered by applying the strain boosters, such as SiN stress liner, embedded SiGe or SiC in the S/D region, shallow trench isolation, and S/D silicidation. Among these approaches, SiN capping technique has received much attention because it is easily implemented in modern VLSI technology. In addition, depending on the SiN deposition conditions, the SiN layer can generate either tensile or compressive stress, enabling the dual-SiN stressor technology for CMOS manufacturing. Therefore, in this thesis, we focus on the fabrication and characterization of strained channel MOS devices with SiN capping layer. Although the SiN capping can dramatically enhance the carrier mobility and thus the device drive current, the robustness to hot-carrier and NBTI degradation is compromised as well, owing to the large amount of hydrogen contained in the SiN layer. 8.

(32) by using the hydrogen-containing precursors, i.e., NH3 and SiH4 (or SiH2Cl2), which may diffuse into the channel region during the process. In order to eliminate this shortcoming, in Chapters 2 & 5, the insertion of a thin buffer layer between the gate and the SiN capping layer is proposed to suppress the diffusion of hydrogen species into the channel region, and the result demonstrates that the hot-carrier and NBTI reliabilities can be restored without compromising current enhancement due to the SiN capping. In addition, in Chapter 3, another useful approach is also explored to directly adjust the composition of SiN film by varying precursor gas flow rate and deposition temperature. We successfully develop the SiN film with high tensile stress but low hydrogen content, which is beneficial for NMOSFETs’ performance and hot-carrier reliability. After investigating the device performance enhancement and related reliability issues, we found that increasing tensile stress will result in off-state leakage increase. Therefore, we are devoted to investigate the impact of stress induced by SiN capping on the leakage current in Chapter 4. In addition, flicker noise is very important for low frequency analog circuits and rf applications; however, very few literatures have paid attention to its study on the strained channel device. Therefore, the impacts of SiN-capped NMOSFETs on the flicker noise characteristics are investigated in Chapter 6.. 1.3 Thesis Organization This dissertation is divided into seven chapters. In Chapter 1, the backgrounds and motivations of the thesis are reviewed. In Chapter 2, a novel scheme involving the insertion of a thin buffer layer between the gate and the SiN layer is proposed and demonstrated to restore the hot-carrier reliability of the SiN-capped devices without compromising the current enhancement 9.

(33) due to the SiN capping. Bandgap narrowing effect induced by SiN capping and the lateral distribution of interface state after hot-carrier stress are also investigated. In Chapter 3, the strained n- and p-channel MOSFETs with different types of SiN film by varying the N2 flow rate and deposition temperature during the deposition step are fabricated and characterized. X-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectrometer (FTIR), and film stress measurement system are applied to analyze the properties of the SiN films. We found that tensile stress increases with increasing N2 flow rate, therefore boosting the NMOSFETs’ performance. In addition, the increase in N2 flow rate and deposition temperature tends to weaken the signal of Si-H bonds. Finally, the immunity for devices to hot-carrier degradation and NBTI reliability is mainly affected by the hydrogen content, rather than the stress level. In Chapter 4, we have fabricated strained-channel NMOSFETs with different tensile stress by adjusting SiN thickness. The impacts of stress induced by SiN capping on the leakage current are investigated. Gate-induced drain leakage (GIDL) current is identified to be responsible for increased off-state leakage current. In Chapter 5, SiN-capped PMOSFETs with a thin HfO2 buffer layer were fabricated and characterized. HfO2 buffer layer is helpful to mitigate the degradation of NBTI. In addition, AC NBTI stress of devices is further studied. The aggravated NBTI degradation in the SiN-capped devices can be alleviated by high frequency operation, while HfO2-buffered sample still depicts less degradation than SiN-capped sample. In Chapter 6, the impacts of devices with SiN capping layer on the flicker noise characteristics are investigated. Both carrier number fluctuation theory and mobility fluctuation theory are utilized to model the flicker noise. We found that hydrogen species contained in the SiN film play an important role in the flicker noise characteristics.. 10.

(34) In Chapter 7, we conclude with summaries of the experimental results. Recommendations for future research are also given.. 11.

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