1.2.1 Advantages of high-κ gate dielectric
In terms of the electrical design of the device, it is convenient to define an electrical thickness of the high-κ gate dielectric. According to eq. (3), the capacitance could be expressed in terms of teq (equivalent oxide thickness (EOT)) and 3.9 (dielectric constant of SiO2).
high
high
eq EOT t
t 3.9
. (4)
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The term teq represents the theoretical thickness of SiO2 that was required to achieve the same capacitance density as the dielectric. Using high dielectric constant material for gate dielectric could have larger physical thickness and maintain smaller equivalent oxide thickness (EOT), as shown in Fig. 1-3. The direct tunneling current would be decreased due to larger physical thickness. Compared to the high performance microprocessor market, transistors with lower (about 10-3 A/cm2) leakage currents would be required for the rapidly growing market of low-power applications. Fig. 1-4 shows the gate current density and the standby power consumption as a function of gate voltage. Compared to 15 Ǻ oxide, the high-κ gate dielectric with same EOT shows the great reduction of the gate leakage and power consumption. As a result, the gate dielectric with higher permittivity than oxide is required for low power device. In short, high-dielectric-constant (high-κ) thin films have been considered as suitable gate dielectric for modern CMOS technology.
1.2.2 Choice of the high-κ gate dielectric
To minimize the direct tunneling current, the ultrathin silicon oxynitride (SiON) is a solution to replace silicon oxide (SiO2) when conventional oxide cannot be scaled down. Several researches focus on applying different methods to optimize the quality of ultrathin oxynitride to substitute conventional oxide since 1990 [12]-[15]. It has been reported that oxynitride has ability to prevent boron diffusion from gate electrode to substrate in pMOSFETs [16, 17], suppress the hot-carrier degradation and enhance electron mobility in nMOSFETs [18, 19], and reduce the equivalent oxide thickness or leakage current [20, 21]. The dielectric permittivity () of oxynitride depends on its content of nitrogen. Unfortunately, the oxynitride only extends the gate dielectric two or three (90-40nm) generations because the value is not higher enough. As a result, high- material becomes a candidate to replace conventional
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oxide and oxynitride. The principle of choosing the high- material is described as follows [22]:
(a) The κ value must be high enough.
Table 1-1 shows the main high-κ gate dielectric materials with their parameters:
ε is the permittivity, Eg is the band gap, CBO is the conduction band offset, and VBO is the valence band offset [23]. Fig. 1-5 depicts the relation between the κ value and the dielectric band gap [24]. It can be seen that the κ value tends to vary inversely with the band gap. The first requirement is the κ value should be over 12. There are numerous dielectrics with extremely large κ value, but with unsuitable low band gap.
Furthermore, a very large κ is undesirable in CMOS design due to undesirable fringing fields at the source and drain electrode [25]. Consequently, the dielectric, such as HfO2, ZrO2, and La2O3, with κ value within 25-30 is preferable in CMOS technology.
(b) High-κ dielectric should be thermodynamically stable with Si channel.
There usually have extensive inter-diffusion effects or chemical reactions when direct growing high-κ gate dielectric on silicon substrate, resulting in the properties degradation of the gate dielectric, the underlying silicon, or both [26]. The required property of the dielectrics is that it must not react with Si forming either SiO2 or silicide according to the unbalanced reactions
2
2 Si M SiO
MO , (5)
2
2 2Si MSi SiO
MO . (6) This reason is that forming SiO2 layer would increase the EOT and negate the effect of using high-κ gate dielectric, whereas forming silicide (eq. (6)) would short out the
6 field effect.
It could be used a ternary phase diagram with tie lines to represent the stability of a gate dielectric in contact with Si, as shown in Fig. 1-6. Tie lines which connect two compositions represent that they could be with each other in equilibrium [22]. As shown in Fig. 1-6(a) and Fig. 1-6(b), MOx could not directly connect to Si unless via the SiO2, for example Ta2O5 or TiO2. On the other hand, metal oxide dominant type shown in Fig. 1-6(c) has a tie line between MOx and Si, which means that high-κ metal oxides could direct connect to Si, such as ZrO2. In short, it should be focus on metal oxide dominant type for choosing high-κ materials, like ZrO2, HfO2, Al2O3, Y2O3, La2O3, Sc2O3 and some lanthanides such as Pr2O3, Gd2O3 and Lu2O3.
(c) Higher energy band gap and conduction band offset with Si should over 1 eV.
The high-κ material should act as a gate insulator in MOS structure. In that case, it requires that the potential barrier at each band must be over 1 eV so that could inhibit conduction by the Schottky emission of electrons or holes into the oxide band [24], as shown schematically in Fig. 1-7. Fig. 1-8 depicts the calculated conduction band and valence band offsets of various oxide on Si. In general, the conduction band offset is usually smaller than the valence band offset; therefore, the limits of the choice on high-κ material should with band gap over 5 eV. The high-κ material such as ZrO2, HfO2, Al2O3, Y2O3, La2O3 and various lanthanides and their silicates and aluminates could satisfy this criterion.
(d) Interface quality
The oxide is directly contact with Si channel, while the carriers in the channel flow within angstroms of the Si-oxide interface. Therefore, the interface must be the highest electrical quality; in other words, the interface should have less roughness and
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(e) Defects
Defects in the dielectric are the electronic states in the band gap of the oxide, which are usually generated by oxygen vacancies or impurities. There are some reasons that defects are undesirable and should be greatly reduced. First, charge trapped in the defects states in the oxide band gap and would change with time, resulting in the threshold voltage shift and instability of operation voltage. Second, the trapped charge in the defect would induce carrier scattering within the channel, leading to carrier mobility degradation. Third, defects cause the electrical reliability problems of the devices, such as hysteresis, breakdown, hot-carrier stress (HCS), stress-induced leakage current (SILC), time dependent dielectric breakdown (TDDB), positive bias temperature instability (PBTI), and negative bias temperature instability (NBTI).
1.2.3 Hf-based high-κ gate dielectric
In order to replace conventional SiO2 as a gate dielectric thin film, high-κ materials have been investigated, such as ZrO2 [27-29], HfO2 [30-32], Ta2O5 [33], TiO2 [34-36], Y2O3 [37-39], Al2O3 [40, 41], La2O3 [42]. Ta2O5 and TiO2 have too low conduction band offset with Si, thus the leakage current is sensitive to temperature.
Al2O3 has the disadvantage of a rather low κ value, whereas Y2O3 has not only lower κ value than HfO2 but also poor thermal stability due to heavily reactive with Si.
La2O3 has a slightly higher κ than HfO2, it is hygroscopic though. Although ZrO2 and HfO2 are both generally believed to be two good materials for high-κ gate dielectric, it was found that ZrO2 was slightly reactive with Si forming the silicide ZrSi2 [22]. For this reason, HfO2 was presently the preferred high-κ gate dielectric over ZrO2.
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In short, HfO2 is a promising gate dielectric layer because it has high dielectric constant (κ ~ 25), relatively large band gap (Eg ~ 5.7 eV), large conduction band offset with Si (~1.5 eV), and stable contact with Si.