Homodyne and Heterodyne Comparison

After introducing both homodyne and heterodyne systems, here is the reason that

the heterodyne system is used for optical operation in this thesis. Essentially, the

homodyne system determines the intensity ratio of laser sourceI t_O( ) and interference

fringes (For example,

I t in equation (1.7)). The homodyne is a method with a

_A( )

great potential because its resolution depends on ADC output bits [4] and without the

physical restriction in Doppler frequency, that means state-of-the-art electronics in

ADC or other mixed-signal circuits can help the improving in both position resolution

and velocity tolerance. But some realization problems may affect the signal integrity.

In realization, the intensity of bothI t_O( )and ( )

I t must be in a stable range and the

_A

photodetector must have a good signal to noise ratio to keep the optical intensity

transferring to the electronic signal correctly. Besides, to setup a homodyne system

must challenge the following problem. (1) The measurement and reference beam

overlap changes during motion; this makes the optical alignment facing a critical

challenge or scarifies the coherence of interference fringes and loss the integrity in

displacement, as shown in Figure 1.8 [12]. (2) Non-ideal characteristics of

photodetectors, this may affect the intensity and produce the fault signal [12]. (3)

When doing the multi-axes measurement, the laser source intensityI t_O( )must be

distributed to each axis equally; this makes the optical setup more complicated or

needs to use multiple laser sources to finish the multi-axes setup [12].

The heterodyne systems do not need the careful regard for the beam intensity. Since

the Doppler frequency fD is carried on light central frequency produced by either

Zeeman effect or AOM, the heterodyne systems care about the timing accuracy in

each measurement cycle. The heterodyne systems also have weakness in resolve the

displacement and velocity. To resolve the timing more accurate, the counting clock

frequency must be multiple times faster then the reference/central signal. The slow

reference frequency can have a better timing resolution intuitively, but the excessively

slow reference frequency will limit the target speed away from the photodetector,

which produces negative Doppler frequency.

0 1 2 3 4 5 6 7 -1

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

N o rm al iz ed A m pl itud e

Displacement

Ideal Alignment Misalignment

Figure 1.8 Effect on homodyne misalignment

To compromise the benefits and drawbacks of these two optical operations, this

thesis chooses the heterodyne systems to assure the information integrity under a

critical environment and inexpert optical alignment. Then increase the timing

resolution by digital circuits’ technique.

Chapter 2 Electronics of Heterodyne Laser Interferometer

2.1 Basic Operation

The basic phase estimation of heterodyne laser signal is to put on a counter and

count the cycle between the rising edges of measurement and reference signal, like the

T

1

Δ in Figure 2.1 [14]. The phase change between cycles in Figure 2.1 isΔ

T

₂-Δ ,

T

₁

accumulates the phase change continuously, and the total phase displacement can be

determined. There still has problem in the determination ofΔ and

T

₁ Δ , for example,

T

₂

what if theΔ or

T

₁ Δ is equal to 0? The control unit of the counter may have the

T

₂

ambiguity whether it should reset the counter or not. The feasible method to estimate

the phase change is to place two counters to determine

T and

_M

T respectively, and

_R

subtract

T from

_R

T .Since

_M

T is almost a constant if the laser source frequency is stable

_R

enough, the interface updates the accumulating phase every rising edge of

measurement signal. The control unit will feel comfortable in this method and process

less error during the estimation of the phase variation.

Since the prototype of phase calculation is almost finished. There still has challenge

between the timing resolution and the limitation on the digital circuits. As discussed

before, the faster clock results the higher resolution on resolving every measurement

signal, but the digital counter can not afford the fast clock as higher resolution

expecting. Even the advanced lithography process progress everyday, the fast clock

also produces consideration power consumption and increase the chip temperature.

The following are several ways proposed to extend the timing resolution without

increasing the clock speed. In the following discussions, the integral part means the

multiple counts of the fast clock in Figure 2.1; the fraction part means the time

interval in one fast clock period that is determined.

T2 1 Δ

ΔT

1

1 360 360

R

T f N

ϕ = °^ΔT = ° Δτ

TR

TM

Figure 2.1 Basic Phase Estimation diagram.

2.2 Delay Line Interpolator

The delay line interpolator method is proposed in 1998 by F.C. Demarest and Zygo

Corporation [15]. As shown in Figure 2.2, the fast clock is generated from PLL and 20

MHz reference signal FR. This PLL generates two clocks; one is 1280 MHz for the

counter to evaluate the integral part of the timing register, and the other is 40 MHz for

circuits processing. The 1280 MHz counter clock feeds into the delay locked loop

which has eight stages delay line. When the DLL lock the period of the 1280 MHz

clock, the same control voltage which is exported from the loop filter attaches on the

slave delay line and produces the same delay in the delay line interpolator.

Figure 2.2 The block diagram of Zygo delay line interpolator.

The slave delay line has the same delay behavior to the master delay line produced

by the master delay line. When the measurement signal enters into the delay

interpolator, the interpolator generates eight signals which have the delay to each

other in one of eight period of the counter clock. As shown in Figure 2.3 [16], when

the measurement signal occur a rising edge trigger, the control unit indicates the

counter clock to capture the output of delay line interpolator. The captured pattern can

represent the location where the measurement signal triggers in the previous counter

clock cycle. If the measurement clock is ideally close to the previous clock rising

edge trigger, the next clock trigger captures the pattern totally 1. And another situation,

if the clock triggers at just half of the clock period in the previous clock, the next

clock trigger will capture the pattern ‘11110000’. After the right code conversion, the

captured pattern can represent the fractional part in one clock period. By this skillful

method, it can obviously detect the timing under one clock cycle and have the eighth

resolution than just use the fast clock from PLL.

Counter Clock 1280 MHz

Measurement Signal

captured pattern "11000000"

Figure 2.3 The operation diagram of Zygo delay line interpolator.

2.3 Two-way Frequency-Conversion

The homodyne technique has the problem in intensity and direction ambiguity, and

heterodyne technique has the restricted bandwidth by central frequency and resolution

specification. For example, the digital phase meter resolves the timing to 1ns; the

corresponding angular resolution is 0.36° in 1 MHz reference frequency. But the same

1ns, it only resolves to 3.6° in 10 MHz carrier signal. One way to increase the

resolution is to shift the measurement and reference signal in a lower level, as shown

in Figure 2.4 [14]. In Figure 2.4, the dropped heterodyne beat frequency

f causes the

_b

narrow bandwidth in negative Doppler frequency.

The solution to this problem is to generate a signal which converts the Doppler

frequency to a contrary direction.

fb

Figure 2.4 Frequency conversion diagram.

As shown in Figure 2.5 [14], the measurement signal which carries the Doppler

frequency pass through a power splitter and mixed with two frequencies,

f

_b+ ,

f

and

f

_b+ . The mixed signals have the identical carrier frequency f, and the Doppler

f

frequency fΔ have the same quantity but the opposite sign. The phasemeters digitalize

the Doppler frequency both fΔ and- fΔ . Since these dual frequencies can be detected,

Δf is obtained when fΔ is quite less than zero.

The converted Doppler frequencies have opposite sign in analog operation. A

switching circuit is used to select the right fΔ information. Shown in Figure 2.6 [14],

when the target has a positive velocity, the phasemeter A continuously unwrap the

information from the signal. When the velocity drops the zero, the phasemeter B starts

Figure 2.5 Two-way frequency conversion diagram.

to read the signal

and determines the fΔ . When the frequency is lower than -2/3f, which is the lowest

end that phasemeter A can detect, the switching circuit reads the data from phasemeter

B to phase accumulator to continue the unwrapping operation.

Figure 2.6 Phasemeters selection diagram.

(q r )

Y p L

M MN

= + +

Figure 2.7 Mechanical Vernier Scale.

2.4 Vernier Scale

As its name, the Vernier scale method is developed from the mechanical Vernier

caliper [17]. Figure 2.7 shows the operation of the Vernier caliper. The unit length L is

divided into the equal segments which number is N and the stripes are inscribed on

the Vernier scale. The same length L in the main scale is divided into M divisions

(where M = cN – 1, c is a positive integer and is equal to 2 here). The resolution in

Figure 2.7 is L/(MN), and L in Figure 2.7 is 39 mm, M is 39, N is 20. The measured

length Y is:

The Vernier scale method is that assuming the incoming measurement and reference

signal has the same or very close period. The common period can be viewed as the

unit length L in the previous discussion. Pass the reference signal into a PLL and

multiply the frequency by M, so the generated clock has M divisions in one reference

6 4 Lead the Main Clock Fractional Part is

1 Integral part is

Figure 2.8 The operation of Vernier scale method.

period. The measurement signal is passed through another PLL and generates another

clock which has N divisions in one measurement or nearly reference period. The

operation diagram is shown on. The main clock determines the integral part of the

phase difference. When the Vernier clock triggers, it begins to determine the fractional

part. Every Vernier clock period, the Vernier clock chases upon the main clock in

1/MN period of the reference signal [17]. The counts that Vernier clock chases is the

residual timing between the last main clocks trigger and the measurement signal

triggers in 1/MN resolution of the reference signal. In Figure 2.8 [17], the main clock

has the frequency M times that reference signal, and the Vernier clock has N times

than the measurement signal. The main clock begins to count the integral part when

the reference signal triggers. The counter counts to 1 when the measurement signal

comes up, so the integral part is 1/M. There still has time interval between the last

main clock triggers and the measurement signal rises. The following operation makes

the Vernier clock trigger detect the high low level of the main clock. Once the Vernier

clock overheads the main clock, it means the undetermined time interval of main

clock has been count in 1/MN (here the fractional part is 3/MN).

The Vernier scale method increases the resolution tremendously, but the lack of

velocity tolerance makes it difficult to realize on the servo control system. The reason

is that the moving target mirror affects both measurement signal and the Vernier clock

which is generated from the measurement signal and PLL. That means the moving

target mirror causes the jitter and undetermined timing during the fractional counting.

The previous research specify the restriction of the frequency deviation as the N times

of the Vernier clock, the vmax can be derived as below [18]:

The resolution is limited by the ts which is the settling time of the detecting flip-flop,

and the b can be estimated as b = ts

f

max, where the fmax is the maximum reference

frequency that the chip or device can work properly. This work is accomplished with

0.6 nm displacement resolution (with λ/2 linear interferometer), ± 0.3 m/sec target

speed.

2 max

( ) , where 1 2 ^ref

v f b b

N

≈

λ

= ^(2.2)

Chapter 3 Architecture

3.1 Octonary Phase Interpolation

This method is the reverse of the Zygo delay line interpolator which delays the

measurement signal in one of eight of fast clock period. The PLL in this operation

generates eight phases’ signals of the fast clock. When the measurement signals

triggers, it outputs the pattern of these eight phase clocks’ high-low level, and if the

phases is generated precisely, the trigger location below one clock cycle can be

located in anyone of eight patterns in one clock period.

As shown in Figure 3.1. The measurement signal export the pattern from the eight

phase clocks. The 8-bits number then pass through a code converter and transform to

One clock period

"01111000"

Output pattern Measurement Signal

Eight Phase Clocks

a 3-bits number which represents the read phase location from 0 to 7.

Subtracting the previous measurement cycle’s phase location from the new read

ones induces the phase difference below one clock period between two measurement

cycles. This difference is employed as the fractional part of one measurement

counting, and expanding the timing determination sub clock.

3.2 Data path of Integer Part Calculation

The integer part time counting is to count the measurement signal period by a faster

clock, the counts can represent the time ought to the measurement signal period with

8 3 3

Phase Pattern

Phase Location

Subtractor

Fractional Part Counts 3

Figure 3.2 Fractional Part Determination.

Figure 3.3 The control unit of the Integer part calculation.

the timing resolution in one faster clock period. As shown in Figure 3.3, the idle state

is S_0, and when the measurement comes to 1, the state machine generates three

pulses sequentially, which first outputs counter’s value in that time, and then reset the

counter, finally outputs the fractional part value. When the measurement goes down to

0, the circuits accumulate the counts as the incremental phase difference. During the

pass and reset process, the circuits do not count the time even the measurement signal

is in high voltage level. Due to this situation, the real integer counts are the counter’s

counts plus 2.

In Figure 3.5, a trouble appears when the circuits are implemented on the FPGA.

Since the counts’ integral and fractional part is calculated separately. The

meta-stability problem of the integral part counter induces the value instability even

the frequency varies within one clock period. This problem drops the time resolution

to one clock period, and the fractional part detect is useless because the integral part

varies an extra count and the frequency do not change so. The following sections

propose several ideas to solve this problem and guarantee the time resolution under a

Figure 3.4 The save and reset timing diagram of the control unit.

clock period.

3.3 Multiplexer Determination

In previous sections, a counter module with save-and-reset action is represented as

an int_counter module as in Figure 3.6. Eight int_counter modules are employed and

connect with eight different phases of clocks, and each of them counts the same

measurement signal.

Figure 3.5 The integral parts counts change unstably.

Control Unit

Measurement Signal

Clock

Reset Counter

Counts Register

32 32

Output the counts

int_counter module

32 Measurement Signal

Clock

Figure 3.6 A counter module with save-and-reset control unit.

In ideal case, the output counts register has a corresponding relationship with the

fractional part value. As depicted in Figure 3.7, the count_reg_0 to

count_reg_7 are the counts result of eight different phase’s clock which count the

same measurement signal. The 3-bits sel register is the phase location of that cycle’s

measurement trigger. The sel here from 6, 5, to 4 in each measurement cycle, which

reveal the fractional part value is 7. In integral part, one of the eight numbers is 3D

and others seven are 3E. It means there are 7 clocks has triggered before the

measurement signal trigger in the last clock period. This multi-counter calculation

helps us to determine the integral part value more accurate. The first developed

method is to select the counts register by the multiplexer. As shown in Figure 3.7, the

correct register is count_reg_6 where the sel is 5. The less integral number plus

the fractional part constitute the correct frequency estimation. The schematic is shown

as Figure 3.8.

Figure 3.7 count registers’ relationship with the fractional part value.

Although the multiplexer selection looks reasonable, it gets tough to realize on chip.

This architecture can not endure different PVT library, and selection between the

phase location register sel and the correct integral register is mismatch under

different process library. Besides, under the FPGA test, the integral part still vibrates

no matter the register is choose. A revised integral part determination is proposed in

the following section to deal with this problem.

3.4 Minimum Sorter Determination

The multiplexer determination causes plenty of troubles in implementation; the

minimum determination is the improved function to choose the correct integral

register. As shown in Figure 3.7, the correct integral part value is 3D no matter the

Code

Figure 3.8 Schematic of multiplexer determination.

phase location is 6, 5, or 4, and the minimum of the eight integral part values also can

represent the counts from the last beginning clock after the measurement signal trigger.

This method endures the different process corner and performs a better result then the

foregoing. The further formation is to pass the signal into both minimum and

maximum minus 1 block, as shown in Figure 3.9. This arrangement is to prevent the

miscounting situation like in Figure 3.7 if the only minimum register is miscount to

3E. The fractional part is involved again to recognize which register should be

employed. The complete block diagram is shown in Figure 3.9.

The overall architecture is shown in Figure 3.10. The multiply 64 PLL generates the

eight phases’ clocks and synchronizes with the reference signal. The phasemeter

8 3 3

3

Figure 3.9 Schematic of minimum sorter determination

mentioned foregoing calculates the measurement count and outputs the digital words.

The adder adds the constant reference count due to the synchronized reference signal.

The variance between the measurement count and reference count can represent the

velocity output in the moment, and the incremental velocity is the accumulated

displacement since the measurement process starts.

3.5 Metastability and Displacement Resolution Discussion

In practical realization, it only needs four clocks in Figure 3.1 and is enough to

determine eight phase location where the measurement signal triggering. Assume that

the flip-flops’ setup and hold time region are not over eighth of one clock period.

As shown in Figure 3.11, the measurement signal triggers at the rising edge of clk1.

Since the clk2, clk3, and clk4 are stable in this region, the probable location here is

phase location 7 or 0, which is only affected by the metastability in clk1. However, no 64 PLL

×

Figure 3.10 Overall Architecture of the circuits.

matter which location is chosen, the displacement error does not exceed the resolution

that under eighth of one clock period.

The displacement resolution relies on the timing resolution of the reference signal

but not the measurement ones. If the fixed timing resolution is 0.1ns, the displacement

resolution is 0.632 nm if the wavelength is 632 nm and the frequency is 1 MHz. The

resolution rises to 63.2 nm if the frequency is up to 10 MHz. In the heterodyne

interferometry, the displacement resolution is the phase or timing resolution of the

reference signal. The measurement signal’s timing results only represent the time

portion in the reference one. Although the fixed timing resolution may have the more

indistinct resolution in resolving the fast measurement signal’s timing, the counted

measurement portions under the reference signal phase resolution does not affect or

drop the resolution of displacement.

One clock period

Figure 3.11 The probable determined phase location when the timing violation occurs.

3.6 Method comparison

The Zygo delay line interpolator has a good performance including the high

displacement resolution under a clock period and high velocity tolerance of target

mirror, but it requires more sophisticated analog components (one PLL, one DLL, and

one delay line) to cooperate and finishes the work. The frequency shift method has a

great advancement in displacement resolution and hold on the tolerance in mirror

translation velocity, but it also needs lots of analog component such as mixers,

diplexers, and frequency synthesizers to generate precise frequency in local oscillator

parts of Figure 2.5 [14]. The frequency of local oscillator needs the precise adjustment

or it makes error in calculating the displacement.

or it makes error in calculating the displacement.

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