Chapter 2 Electronics of Heterodyne Laser Interferometer
2.4 Vernier Scale
As its name, the Vernier scale method is developed from the mechanical Vernier
caliper [17]. Figure 2.7 shows the operation of the Vernier caliper. The unit length L is
divided into the equal segments which number is N and the stripes are inscribed on
the Vernier scale. The same length L in the main scale is divided into M divisions
(where M = cN – 1, c is a positive integer and is equal to 2 here). The resolution in
Figure 2.7 is L/(MN), and L in Figure 2.7 is 39 mm, M is 39, N is 20. The measured
length Y is:
The Vernier scale method is that assuming the incoming measurement and reference
signal has the same or very close period. The common period can be viewed as the
unit length L in the previous discussion. Pass the reference signal into a PLL and
multiply the frequency by M, so the generated clock has M divisions in one reference
6 4 Lead the Main Clock Fractional Part is
1 Integral part is
Figure 2.8 The operation of Vernier scale method.
period. The measurement signal is passed through another PLL and generates another
clock which has N divisions in one measurement or nearly reference period. The
operation diagram is shown on. The main clock determines the integral part of the
phase difference. When the Vernier clock triggers, it begins to determine the fractional
part. Every Vernier clock period, the Vernier clock chases upon the main clock in
1/MN period of the reference signal [17]. The counts that Vernier clock chases is the
residual timing between the last main clocks trigger and the measurement signal
triggers in 1/MN resolution of the reference signal. In Figure 2.8 [17], the main clock
has the frequency M times that reference signal, and the Vernier clock has N times
than the measurement signal. The main clock begins to count the integral part when
the reference signal triggers. The counter counts to 1 when the measurement signal
comes up, so the integral part is 1/M. There still has time interval between the last
main clock triggers and the measurement signal rises. The following operation makes
the Vernier clock trigger detect the high low level of the main clock. Once the Vernier
clock overheads the main clock, it means the undetermined time interval of main
clock has been count in 1/MN (here the fractional part is 3/MN).
The Vernier scale method increases the resolution tremendously, but the lack of
velocity tolerance makes it difficult to realize on the servo control system. The reason
is that the moving target mirror affects both measurement signal and the Vernier clock
which is generated from the measurement signal and PLL. That means the moving
target mirror causes the jitter and undetermined timing during the fractional counting.
The previous research specify the restriction of the frequency deviation as the N times
of the Vernier clock, the vmax can be derived as below [18]:
The resolution is limited by the ts which is the settling time of the detecting flip-flop,
and the b can be estimated as b = ts
f
max, where the fmax is the maximum referencefrequency that the chip or device can work properly. This work is accomplished with
0.6 nm displacement resolution (with λ/2 linear interferometer), ± 0.3 m/sec target
speed.
2 max
( ) , where 1 2 ref
v f b b
N
≈
λ
= (2.2)Chapter 3 Architecture
3.1 Octonary Phase Interpolation
This method is the reverse of the Zygo delay line interpolator which delays the
measurement signal in one of eight of fast clock period. The PLL in this operation
generates eight phases’ signals of the fast clock. When the measurement signals
triggers, it outputs the pattern of these eight phase clocks’ high-low level, and if the
phases is generated precisely, the trigger location below one clock cycle can be
located in anyone of eight patterns in one clock period.
As shown in Figure 3.1. The measurement signal export the pattern from the eight
phase clocks. The 8-bits number then pass through a code converter and transform to
One clock period
"01111000"
Output pattern Measurement Signal
Eight Phase Clocks
a 3-bits number which represents the read phase location from 0 to 7.
Subtracting the previous measurement cycle’s phase location from the new read
ones induces the phase difference below one clock period between two measurement
cycles. This difference is employed as the fractional part of one measurement
counting, and expanding the timing determination sub clock.
3.2 Data path of Integer Part Calculation
The integer part time counting is to count the measurement signal period by a faster
clock, the counts can represent the time ought to the measurement signal period with
8 3 3
Phase Pattern
Phase Location
Subtractor
Fractional Part Counts 3
Figure 3.2 Fractional Part Determination.
Figure 3.3 The control unit of the Integer part calculation.
the timing resolution in one faster clock period. As shown in Figure 3.3, the idle state
is S_0, and when the measurement comes to 1, the state machine generates three
pulses sequentially, which first outputs counter’s value in that time, and then reset the
counter, finally outputs the fractional part value. When the measurement goes down to
0, the circuits accumulate the counts as the incremental phase difference. During the
pass and reset process, the circuits do not count the time even the measurement signal
is in high voltage level. Due to this situation, the real integer counts are the counter’s
counts plus 2.
In Figure 3.5, a trouble appears when the circuits are implemented on the FPGA.
Since the counts’ integral and fractional part is calculated separately. The
meta-stability problem of the integral part counter induces the value instability even
the frequency varies within one clock period. This problem drops the time resolution
to one clock period, and the fractional part detect is useless because the integral part
varies an extra count and the frequency do not change so. The following sections
propose several ideas to solve this problem and guarantee the time resolution under a
Figure 3.4 The save and reset timing diagram of the control unit.
clock period.
3.3 Multiplexer Determination
In previous sections, a counter module with save-and-reset action is represented as
an int_counter module as in Figure 3.6. Eight int_counter modules are employed and
connect with eight different phases of clocks, and each of them counts the same
measurement signal.
Figure 3.5 The integral parts counts change unstably.
Control Unit
Measurement Signal
Clock
Reset Counter
Counts Register
32 32
Output the counts
int_counter module
32 Measurement Signal
Clock
Figure 3.6 A counter module with save-and-reset control unit.
In ideal case, the output counts register has a corresponding relationship with the
fractional part value. As depicted in Figure 3.7, the count_reg_0 to
count_reg_7 are the counts result of eight different phase’s clock which count the
same measurement signal. The 3-bits sel register is the phase location of that cycle’s
measurement trigger. The sel here from 6, 5, to 4 in each measurement cycle, which
reveal the fractional part value is 7. In integral part, one of the eight numbers is 3D
and others seven are 3E. It means there are 7 clocks has triggered before the
measurement signal trigger in the last clock period. This multi-counter calculation
helps us to determine the integral part value more accurate. The first developed
method is to select the counts register by the multiplexer. As shown in Figure 3.7, the
correct register is count_reg_6 where the sel is 5. The less integral number plus
the fractional part constitute the correct frequency estimation. The schematic is shown
as Figure 3.8.
Figure 3.7 count registers’ relationship with the fractional part value.
Although the multiplexer selection looks reasonable, it gets tough to realize on chip.
This architecture can not endure different PVT library, and selection between the
phase location register sel and the correct integral register is mismatch under
different process library. Besides, under the FPGA test, the integral part still vibrates
no matter the register is choose. A revised integral part determination is proposed in
the following section to deal with this problem.
3.4 Minimum Sorter Determination
The multiplexer determination causes plenty of troubles in implementation; the
minimum determination is the improved function to choose the correct integral
register. As shown in Figure 3.7, the correct integral part value is 3D no matter the
Code
Figure 3.8 Schematic of multiplexer determination.
phase location is 6, 5, or 4, and the minimum of the eight integral part values also can
represent the counts from the last beginning clock after the measurement signal trigger.
This method endures the different process corner and performs a better result then the
foregoing. The further formation is to pass the signal into both minimum and
maximum minus 1 block, as shown in Figure 3.9. This arrangement is to prevent the
miscounting situation like in Figure 3.7 if the only minimum register is miscount to
3E. The fractional part is involved again to recognize which register should be
employed. The complete block diagram is shown in Figure 3.9.
The overall architecture is shown in Figure 3.10. The multiply 64 PLL generates the
eight phases’ clocks and synchronizes with the reference signal. The phasemeter
8 3 3
3
Figure 3.9 Schematic of minimum sorter determination
mentioned foregoing calculates the measurement count and outputs the digital words.
The adder adds the constant reference count due to the synchronized reference signal.
The variance between the measurement count and reference count can represent the
velocity output in the moment, and the incremental velocity is the accumulated
displacement since the measurement process starts.
3.5 Metastability and Displacement Resolution Discussion
In practical realization, it only needs four clocks in Figure 3.1 and is enough to
determine eight phase location where the measurement signal triggering. Assume that
the flip-flops’ setup and hold time region are not over eighth of one clock period.
As shown in Figure 3.11, the measurement signal triggers at the rising edge of clk1.
Since the clk2, clk3, and clk4 are stable in this region, the probable location here is
phase location 7 or 0, which is only affected by the metastability in clk1. However, no 64 PLL
×
Figure 3.10 Overall Architecture of the circuits.
matter which location is chosen, the displacement error does not exceed the resolution
that under eighth of one clock period.
The displacement resolution relies on the timing resolution of the reference signal
but not the measurement ones. If the fixed timing resolution is 0.1ns, the displacement
resolution is 0.632 nm if the wavelength is 632 nm and the frequency is 1 MHz. The
resolution rises to 63.2 nm if the frequency is up to 10 MHz. In the heterodyne
interferometry, the displacement resolution is the phase or timing resolution of the
reference signal. The measurement signal’s timing results only represent the time
portion in the reference one. Although the fixed timing resolution may have the more
indistinct resolution in resolving the fast measurement signal’s timing, the counted
measurement portions under the reference signal phase resolution does not affect or
drop the resolution of displacement.
One clock period
Figure 3.11 The probable determined phase location when the timing violation occurs.
3.6 Method comparison
The Zygo delay line interpolator has a good performance including the high
displacement resolution under a clock period and high velocity tolerance of target
mirror, but it requires more sophisticated analog components (one PLL, one DLL, and
one delay line) to cooperate and finishes the work. The frequency shift method has a
great advancement in displacement resolution and hold on the tolerance in mirror
translation velocity, but it also needs lots of analog component such as mixers,
diplexers, and frequency synthesizers to generate precise frequency in local oscillator
parts of Figure 2.5 [14]. The frequency of local oscillator needs the precise adjustment
or it makes error in calculating the displacement.
The Vernier scale method needs less analog components (two PLLs) to achieve high
displacement resolution. But the measurement signal induces the clock unstable
troubles and restricts the mirror translating speed to 0.3 m/s.
The self-developed octonary interpolator provides a digital architecture to solve this
problem with less analog components (one eight phase PLL), and make it easy to
implement entire measuring system in a FPGA board (Altera Cyclone III FPGA). The
following is the comparison of several heterodyne electronics.
Table 3.1 Comparison of Heterodyne Electronics
3.7 Gate Level Simulation on TSMC 0.18 μm Design Kits
To simulate and test the interferometer digital circuits, a method is to employee a
variable wave to simulate the effect of Doppler frequency. If the circuits can detect the
measurement frequency indeed, the variance between it and reference frequency can
be detected. Displacement and speed of the target mirror can also obtain.
The testbench sets the reference frequency as 4 MHz for Agilent Laser Head 5517D
which frequency ranges from 3 MHz to 4 MHz, and multiply the clock frequency up
to 256 MHz. Cooperating with the octonary phase interpolator, the total displacement
resolution compromises to λ/512, λ is the wavelength of laser and comes to 632 nm in
vacuum. The measurement frequency is set as a frequency variant signal, which varies
Mea. Sci.
Position Resolution
λ/512 λ/1024 λ/512 λ/1024 Function generator testing:λ/64
On-chip PLL testing:
λ/512
Speed Tolerance in
Target Mirror
(8 phase output.)measurement triggering, the frequency variance is set as a fractional number which
denominator is 512.
The testbench of this simulation and the detailed measurement profile is shown in
Table 3.2. As shown in Figure 3.13, the pictures show the circuits work properly
during every measurement frequency changes. Equation (3.1) shows the relationship
between the measurement period and the detected integral and fractional value. The
measurement period is modulated with (any value/512), which means the minimum
timing resolution under this architecture is 1/512 of reference period. The integral part
is determined by the counter which has clock speed 64 times than reference period.
The resolution of the integral part is 1/64 of reference period. The fractional part is the
eight phase interpolator of one clock period, which has 8 times timing resolution than
the clock speed, also as 1/512 of reference period time resolution.
( ) ( 2) ( )
512 64 512
ref ref
ref
T T
any value
T
× = ×Integral
+ +fractional
(3.1)Table 3.2 Testbench for gate-level simulation on TSMC 0.18 μm design kits.
The first simulation result is in typical model, as shown in Figure 3.12. Table 3.3
shows the signal index of each signal. The corresponding counts appears clearly with
the measurement frequency change even the variance is small. Figure 3.13 and Figure
3.14 are the zoom-in figures from Figure 3.12. The detailed signals like the state
machine are shown and the correct integral part can be determined without error. The
fractional part is also shown as predicted. Figure 3.15 shows the simulation results in
slow and fast model. During the simulation in slow model, most phase location cannot
be ascertained due to the timing violation between measurement trigger and the clocks
transition. It means the chip cannot work in the difficult environment or the mistakes
Library
TSMC 0.18 μmArea
870938.515625 μm2Clocks
Eight 256 MHz clockswith 45° difference
Displacement Resolution
λ/512Reference Frequency
4 MHzMeasurement Frequency
typical model.
Mea_clk
Measurement Frequency.Clk[7:0]
Eight different phase clocks.Count_sub[31:0]
The value the subtract measurement counts from the reference counts.Count_reg
The selected integral parts by combination logicsCount_reg_0[31:0]
Integral parts of measurement countssynchronized with clk[0].
Count_reg_1[31:0]
Integral parts of measurement counts synchronized with clk[1].Count_reg_2[31:0]
Integral parts of measurement counts synchronized with clk[2].Count_reg_3[31:0]
Integral parts of measurement counts synchronized with clk[3].Count_reg_4[31:0]
Integral parts of measurement counts synchronized with clk[4].Count_reg_5[31:0]
Integral parts of measurement counts synchronized with clk[5].Count_reg_6[31:0]
Integral parts of measurement counts synchronized with clk[6].Count_reg_7[31:0]
Integral parts of measurement counts synchronized with clk[7].Fraction[2:0]
Fractional parts of measurement countsSel[2:0]
Phase Location of measurement triggerTotal_count[31:0]
Accumulated phase variance.Total_reset
Reset signal to total_count[31:0] register.Reg_transfer
State 1 of state machine to save the counters’ counts.reset
State 2 of state machine to reset the counters.(Negative trigger.)
Sel_ctrl
State 3 of state machine to shift previous and present phase location.(Negative trigger.)
add
Accumulate the phase difference.Table 3.3 Signal names for gate-level simulation on TSMC cell library
Corresponding Counts From 3D.7 to 3C.6
Corresponding Counts From 3C.6 to 3B.5
Corresponding Counts From 3B.5 to 3A.4
Corresponding Counts From 3A.4 to 39.3
Figure 3.13 The details of the gate-level simulation results from 3D.7 to 39.3.
Corresponding Counts From 39.3 to 38.2
Corresponding Counts From 38.2 to 37.1
Corresponding Counts From 37.1 to 36.0
(a) (b)
Figure 3.15 (a) The gate-level simulation in fast model. (b) Gate-level simulation in slow model.
Chapter 4 FPGA Verification
4.1 Architecture Adapted for Cyclone III
The PLL included in Cyclone III can not lock the input frequency under 4 MHz. To
compromise this situation, the architecture is modified to two phasemeter and
subtracts the measurement count from reference ones. The chip clocks run at 260
MHz and the displacement resolution is around λ/550. The overall architecture is
shown in Figure 4.1. Unlike the other one shown in Figure 3.10, this architecture
counts both reference and measurement signal simultaneously, and synchronizes the
reference count with the measurement part control signal. This setup synchronizes the
reference count which is updated by the reference signal, and avoids the timing
violation due to the different updating frequency.
Figure 4.1 Architecture adapted for Cyclone III FPGA
4.2 Gate-level Simulation and On-chip Testing
Before the experiment, the gate-level simulation provides a platform to verify whether
the design is workable. Here uses Altera® Cyclone® III library and Synopsys® Design
Compiler® for HDL synthesis and delay annotation. The clock speed drops to 32 MHz
due to the conservative delay model. The clock speed rises to 260 MHz on the on-chip
testing. The actual integral value is 8 here when the measurement frequency is equal
to reference frequency, but the calculated value is 6 here. The missed 2 is due to the
save and reset process in the state machine.
Table 4.1 Gate-level Simulation Environment for Cyclone III FPGA
Library
Cyclone IIIArea
N/AClocks
Eight 32 MHz clocks with 45° differenceDisplacement Resolution
λ/64Reference Frequency
4 MHzMeasurement Frequency
Period
Corresponding Integral Value Corresponding Fractional Value250 ns* (127/64)
0xD 7250 ns* (118/64)
0xC 6250 ns* (109/64)
0xB 5250 ns* (100/64)
0xA 4250 ns* (91/64)
0x9 3250 ns* (82/64)
0x8 2250 ns* (73/64)
0x7 1250 ns* (64/64)
0x6 0The following chart splits to two to show the signal index of the reference and
measurement timing diagram.
Table 4.2 Signal names for reference phasemeter on Cyclone III gate-level simulation.
ref_clk
Reference Frequency.Clk[7:0]
Eight different phase clocks.Count_reg_ref[31:0]
The selected integral parts of reference countsCount_reg_0[31:0]
Integral parts of reference countssynchronized with clk[0].
Count_reg_1[31:0]
Integral parts of reference counts synchronized with clk[1].Count_reg_2[31:0]
Integral parts of reference counts synchronized with clk[2].Count_reg_3[31:0]
Integral parts of reference counts synchronized with clk[3].Count_reg_4[31:0]
Integral parts of reference counts synchronized with clk[4].Count_reg_5[31:0]
Integral parts of reference counts synchronized with clk[5].Count_reg_6[31:0]
Integral parts of reference counts synchronized with clk[6].Count_reg_7[31:0]
Integral parts of reference counts synchronized with clk[7].Fraction[2:0]
Fractional parts of reference countsSel[2:0]
Phase Location of reference signal triggerReg_transfer
State 1 of state machine to save the counters’ counts.reset
State 2 of state machine to reset the counters.(Negative trigger.)
Sel_ctrl
State 3 of state machine to shift previous and present phase location.(Negative trigger.)
add
State 0 of state machine to process the integral part counts determination.The timing diagram shown in Figure 4.2 shows the reaction of the output registers
after the measurement signal in Table 4.1 is fed in. The selected integral part value
varies depending on the different measurement signal, and the fractional part also
responds as expecting. The signal index of the Figure 4.2 (a) is same as the Table 3.3.
Although the reference integral part count is less 2 than the actual value which should
be detected, the measurement ones suffer the same situation. After the subtraction for
the frequency determination, the non-ideal issue is canceled and output the correct
frequency information.
As shown in Figure 4.3, the on-chip testing employees a PLL to simulate the variant
measurement frequency. The two PLLs on Cyclone III chip connects to two different
measurement frequency. The two PLLs on Cyclone III chip connects to two different