CHAPTER 3................................................................................................................................... 35
3.2 I MPLEMENTATION & M EASUREMENT
Fig. 44 shows the layout of VGA block and the size is 120um x 79um. There are a PMOS-type VGA, a NMOS-type VGA and a low gain amplifier.
Figure 44 VGA block
The layouts of two Gm block is shown in Fig. 45(a) and Fig. 45(b). Small Gm and large Gm are only different from MOS size and the layout is close small to reduce parasitic capacitance. The size of small Gm is 21um x 22um. The size of large Gm is 24um x 22um.
(a) Small Gm block (2) Big Gm block3 Figure 45 Two kind of Gm block
(a) LPF block
Figure 46 LPF circuit layout
(a) Layout of Topology(1) (a) Layout of Topology(2) Figure 47 Analog baseband circuit layout
The layout of LPF block is shown in Fig. 46. The size of LPF is 463.1um x 273.6um. The layout of analog baseband circuit layout of topology(2) is shown in Fig.
47(b). In order to reduce area, a switch is added before buffer to switch the first VGA output or total circuit output to characterize the output signal of VGA. The layout of analog baseband circuit layout of topology(1) is showed in Fig. 47(a)
Figure 48 Test setup
Fig. 48 is the testing setup for measuring chip on wafer. In the circuit spectrum analyzer is used to measure frequency response and dynamic range. All of the design are fully-different. A transformer is applied to convert signal after ESG and before Spectrum analyzer.
Fig. 49 show a measurement result of harmonic distortion of the LPF when small Gm is opened and Vcrl=0.4. Because transformer has -8dB loss, 4dBm signal from ESG and LPF receives -4dBm signal for 0.4Vpp. From measurements the pole and zero is shifted the simulation but we can see the LPF still have two zeros. Fig. 50 shows the harmonic distortion measurement result when input signal is 4dBm at 1.73MHz. The dynamic range is limited by the high 2nd tone and is 11dB.
-60 -50 -40 -30 -20 -10 0
0. 51 1. 48 2. 51 3. 01 3. 51 4. 01 4.5 4. 99 6. 01 7. 02 8. 03 8. 97 10 11 12 13 14
MHz
dB
Figure 49 Measurement result of harmonic distortion
Figure 50 Measurement result of harmonic distortion
Several chip samples were measured and recode the -3dB from flat gain in different control voltage. Fig. 51 and Fig. 52 show the result of small and big Gm
respectively. The -3dB frequency is linearity to the control voltage. Because of the parasitic capacitor and the variation of gm cell, the -3dB bandwidth of different chips don’t match the simulation results.
Figure 51 -3dB frequency in different control voltage for small Gm
Figure 52 -3dB frequency in different control voltage for big Gm The comparison between reference publications is shown in Table 13.
Parameters Spec. Topology(1) Topology(2) APMC.2005[6]
Technology CMOS0 .13um CMOS 0.13um CMOS 0.13um CMOS 0.16
Standard WiMax WiMax WiMax WLAN
0.625M~14MHz 0.625B~6.2MHz 0.625B~5.3MHz 7.56 19.5
26.5MHz
Gain range 16dB-86dB 16~86dB 16~86dB 20~60dB
Dynamic
Parameters APMC.2005[7] JSSC.2006[8] TCSI.2006[9]
Technology CMOS0.13um CMOS0.18um CMOS0.13
Standard UMTS
WLAN
WLAN WLAN
UMTS
Power supply 2.5V 1.6-2V 1.2
3-dB bandwidth 3.4~40MHz 2.1,11MHz
Power
Dynamic range 1.4%@ -8dB gain 52(1.4Vpp)
Table 13 Measurement comparison
Chapter 4
Conclusion
The thesis has presented an analog baseband circuit employing a linear-in dB
VGA and a tunable LPF for WiMax. It includes of three 14MHz low power VGA and a tunable bandwidth low power LPF. The novel topology has been applied to the analog front-end for WiMax direct conversion receiver which perform low power, wide dynamic gain range and high data rate. In conclusion, the key contributions presented in previous chapters are summarized below.
4.1 Summary
An optimum arrangement of LPF and VGA for noise figure and interference
trade-off is presented. Two transconductor operating in triode region for a tunable transconductor-C LPF is presented. A linear-in dB topology employing novel pseudo exponential technique for a low power VGA is presented. We use three VGA blocks and a LPF to constitute the analog baseband circuit. The analog baseband circuit
implemented in 0.13-
µ m CMOS process and arrange LPF in second location. The
circuit provides a minimum gain of 16dB and maximum gain of 86dB while drawing 26.8wW from a 1.2-V supply. The dynamic range is 38.19dB for 0.4Vpp. The measurement result of LPF is presented4.2 Future Work
In the thesis, there are some design considerations which we didn’t attention. We give some recommendations and improvement in the section. First the analog baseband design is not optimum. The 2nd and 3rd VGA block gain range can be changed to have larger output swing for total design. The loading of each block didn’t consider comprehensively so the bandwidth was limited. Second the non-ideal resistor of each transconductor is considered too much so the pole and zero will shift from the ideal value and the frequency response will decrease in advance. The layout didn’t consider parasitic capacitors completely. Third the control circuit of the VGA block is only an inverter and DC shift circuit and the better choice is use OP to do control circuit. We didn’t consider best choice is using OP for control circuit. We will make an improvement in the future work.
Bibliography
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