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T OPOLOGY PERFORMANCE ANALYSIS

CHAPTER 2..................................................................................................................................... 7

2.4 T OPOLOGY PERFORMANCE ANALYSIS

Now we can analysis the topologies by VGA and LPF from section 2.2, 2.3.

Table 9 shows the two circuit simulation results.

Block LPF VGA

Bandwidth 0.615M~16.65MHz 14.79MHz

Gain range -10dB 10.3dB~34.4dB

NF(dB) 74.4dB 28.8dB

Dynamic range(0.4Vpp)

>47.38dB >39.81dB

Table 9the simulation result of LPF and VGA

We mainly analyze the noise figure and interference are analyzed to decide which topology can fit the WiMax specification and which have better performance.

From topology(1), LPF arranges in the first stage and A 5-order elliptic LPF can

reject 30dB gain at least. Since the maximum 1 adjacent channel interference C/I is st -21, so the LPF can reject the interference and no VGA stage will be saturated. But the noise figure will be the worst. After simulation the noise figure of topology(1) is 74.4dB.

From topology(2), the maximum 1st adjacent channel interference is -1dBm and

the maximum swing is -4dBm. The interference will be amplified 10.3dB to 9.3dBm and it exceeds -4dBm (0.4Vpp) after a VGA, and the next stage, LPF, will be saturated. At BER 103 the maximum interference is -13dBm which considers -3dB attenuation in RF front end. The interference will be amplified 10dB to -3dBm.

Topology(2) is constrained to be fit the interference specification at BER 103. After simulation the noise figure of topology(2) is 51.87dB.

Only topology(1) can fit the interference requirement at BER 106 and Topology(2) is constrained to fit the interference specification at BER 103 needless to say topology(3) and topology(4).

2.5 Design Optimization for Noise Figure and Distortion Tradeoffs

Topology(1) can reject interference to avoid circuit into saturation but it has bad NF. Topology(2) has better NF but next stage, LPF, may be drove into saturation. The gain of the first stage influences the NF and interference.

Generally a specification will specify the maximum interference that the system can tolerate. When LPF rejectsthe interference that almost saturate LPF, the design is optimization, and can filter out the maximum interference and has best noise figure.

Figure 31 is an analog baseband circuit that has a tunable dB-linearity gain topology and LPF can insert in any location. The circuit can provide A~B dB gain. Each VGA and LPF has the same maximum input and output swing Vm (

V

pp) m dBv. The maximum input signal power is define Vp ( p dBv)

Figure 31 The optimization for noise figure and interference in one LPF and VGAs analog baseband design

Now consider the system receives maximum interference that the system can tolerate. In this time, the signal is maximum and interference is maximum in this worst case. So the gain of circuit will be set to minimal mode A dB. Suppose LPF inserting in location X can filter the interference and that is the optimization. The interference just makes the next VGA into saturation. In this situation, the interference is amplified X dB and has m dBv swing. The adjacent channel interference C/I that the design can tolerate is m – X - p (dBv). The noise figure is

1 1

The noise figure we can improve is Equation (2.11) that Equation(2.10) subtracts Equation(2.9). maximum deference of signal and interference is I. Consider the gain of LNA is 8dB and the attenuation in channel is 3dB.

I = − − m X p

Chapter 3

Simulations and Implementation of Analog baseband

In the chapter we show the simulation result of topology(1) and topology(2).

In the latest tape-out the design uses topology(2) to arrange the VGAs and LPF even though Case(s) can’t satisfy the worst interference specification but it almost can fit the specification at BER 103. The difference between topology(1) and topology(2) is only the position of LPF, so the frequency response and harmonic simulation result will be almost the same. Section 3.1 presents the simulation result of our analog baseband circuit. Sec 3.2 presents the implementation and the measurement result of LPF.

3.1 Simulations for Analog baseband circuit

The last tape-out topology(2) is chosen, but we show the simulation result of two topologies. The VGAs and LPF design have been described in chapter 2.2 and

section.

Figure 32 Dynamic gain range simulation result in topology(1)

0

0.34 0.36 0.38 0.41 0.43 0.45 0.47 0.49 0.51 0.53 0.55 0.57 0.59 0.62 Vtrl

D yn am ic r ange

DR

Figure 33 Dynamic gain range simulation result by harmonic simulation in

topology(1)

Vcr(V) 0.34 0.36 0.38 0.41 0.42.5 0.45 0.47 0.49 0.51 0.53 0.55 0.57 0.59 0.62

Gain(dB) 15.24 21.88 27.3 33.8 39.66 45.45 51.21 56.97 62.73 68.43 74.19 79.25 84.01 88.35

DR(dB) 30.98 38.66 51.82 50.15 50.15 43.42 39.34 38.38 38.5 38.32 38.17 39.73 40.89 42.07

Table 10 The gain and dynamic range simulation result in different control Fig. 32 shows the gain range after we run frequency response in topology(1). Fig.

33 shows the dynamic range simulation result in different control voltage and the output swing is 0.4Vpp. The dynamic range of analog baseband circuit is less than VGA about 2dB.

Figure 34 Frequency responses of analog baseband with small gm in topology(2)

Figure 35 Frequency responses of analog baseband with large gm in topology(2) Fig. 34 and 35 show the frequency response simulation result with small and big respectively. From Fig. 35 we can see the -3dB gain frequency have degraded to about 2MHz. This is because there is a parasitic pole between LPF and VGA. The pole equation is 1

parasitic

LPF LPF VGA

Pole = R C

+

g

R

LPF is the output resistor and

C

LPF VGA+ is the sum of parasitic capacitor of LPF and VGA. So the gain degraded before frequency bandwidth expected.

Figure 36 Frequency response simulation result after adding buffers in topology(1) A buffers is added between LPF and VGA and simulation again. Fig. 36 shows the simulation result and the maximum -3dB frequency is 5.3MHz. The -3dB frequency can’t increase to 14MHz is because the VGA -3dB frequency is 14.79MHz.

The gain of VGA drops before 14MHz. After accumulating two VGA blocks the analog baseaband circuit -3dB frequency will decrease to 5.3MHz.

Figure 37 Dynamic gain range simulation result in topology(2)

0

Figure 38 Dynamic gain range simulation result by harmonic simulation in topology(2)

Figure 39 Dynamic range simulation result in different control voltage in

topology(2)

Vcr(V) 0.35 0.372 0.394 0.416 0.438 0.46 0.482 0.504 0.526 0.548 0.57 0.592 0.614

Gain(dB) 15.44 22.4 28.78 34.9 41.06 47.09 53.14 58.58 65.18 71.03 76.62 81.69 86.69

DR(dB) 31.43 42.61 61.71 45.52 42.03 40.52 38.76 39.72 37.62 38.19 38.36 39.92 41.74

Table 11 The gain and dynamic range simulation result in different control voltage in topology(2)

Figure 40 Output swing simulation with Vcr=460mV

Fig. 37 shows the gain range ac frequency response and Fig. 38 shows the gain range for harmonic simulation with output swing 0.4Vpp in topology(2). Fig. 39 shows the dynamic range simulation result in different control voltage and the output swing is 0.4Vpp too. The transient simulation is shown in Fig. 40. Under the

V =460mV the output swing is 0.4Vpp for differential output with 40dB dynamic

trl

range.

Figure 41 Frequency responses of analog baseband with small gm in topology(2)

Figure 42 Frequency responses of analog baseband with large gm in topology(2) Fig. 41 and 42 show the frequency response simulation result with small and large gm cell in LPF respectively. From Fig. 41 the -3dB gain frequency has degraded about 2.7MHz. Topology(2) has the same problem of topology(1). Fig. 43 shows the simulation result and the maximum -3dB frequency is 5.3MHz after adding buffers

Figure 43 Frequency response simulation result after adding buffers in topology(2)

Parameters Spec. Topology(1) Topology(2)

Technology CMOS 0.13um CMOS 0.13um CMOS 0.13um

Power supply 1.2V 1.2V 1.2V

3-dB bandwidth 0.625M~14MHz 0.625B~5.3MHz 0.625B~5.3MHz Power consumption As small as

possible

7.624mW~26.8mW 7.624mW~26.8mW

NF As small as

possible

84.9dB 51.87dB

Gain range 16dB-86dB 16~86dB 16~86dB

Dynamic Table 12 The simulation results of WiMax analog baseband circuit

3.2 Implementation & Measurement

Fig. 44 shows the layout of VGA block and the size is 120um x 79um. There are a PMOS-type VGA, a NMOS-type VGA and a low gain amplifier.

Figure 44 VGA block

The layouts of two Gm block is shown in Fig. 45(a) and Fig. 45(b). Small Gm and large Gm are only different from MOS size and the layout is close small to reduce parasitic capacitance. The size of small Gm is 21um x 22um. The size of large Gm is 24um x 22um.

(a) Small Gm block (2) Big Gm block3 Figure 45 Two kind of Gm block

(a) LPF block

Figure 46 LPF circuit layout

(a) Layout of Topology(1) (a) Layout of Topology(2) Figure 47 Analog baseband circuit layout

The layout of LPF block is shown in Fig. 46. The size of LPF is 463.1um x 273.6um. The layout of analog baseband circuit layout of topology(2) is shown in Fig.

47(b). In order to reduce area, a switch is added before buffer to switch the first VGA output or total circuit output to characterize the output signal of VGA. The layout of analog baseband circuit layout of topology(1) is showed in Fig. 47(a)

Figure 48 Test setup

Fig. 48 is the testing setup for measuring chip on wafer. In the circuit spectrum analyzer is used to measure frequency response and dynamic range. All of the design are fully-different. A transformer is applied to convert signal after ESG and before Spectrum analyzer.

Fig. 49 show a measurement result of harmonic distortion of the LPF when small Gm is opened and Vcrl=0.4. Because transformer has -8dB loss, 4dBm signal from ESG and LPF receives -4dBm signal for 0.4Vpp. From measurements the pole and zero is shifted the simulation but we can see the LPF still have two zeros. Fig. 50 shows the harmonic distortion measurement result when input signal is 4dBm at 1.73MHz. The dynamic range is limited by the high 2nd tone and is 11dB.

-60 -50 -40 -30 -20 -10 0

0. 51 1. 48 2. 51 3. 01 3. 51 4. 01 4.5 4. 99 6. 01 7. 02 8. 03 8. 97 10 11 12 13 14

MHz

dB

Figure 49 Measurement result of harmonic distortion

Figure 50 Measurement result of harmonic distortion

Several chip samples were measured and recode the -3dB from flat gain in different control voltage. Fig. 51 and Fig. 52 show the result of small and big Gm

respectively. The -3dB frequency is linearity to the control voltage. Because of the parasitic capacitor and the variation of gm cell, the -3dB bandwidth of different chips don’t match the simulation results.

Figure 51 -3dB frequency in different control voltage for small Gm

Figure 52 -3dB frequency in different control voltage for big Gm The comparison between reference publications is shown in Table 13.

Parameters Spec. Topology(1) Topology(2) APMC.2005[6]

Technology CMOS0 .13um CMOS 0.13um CMOS 0.13um CMOS 0.16

Standard WiMax WiMax WiMax WLAN

0.625M~14MHz 0.625B~6.2MHz 0.625B~5.3MHz 7.56 19.5

26.5MHz

Gain range 16dB-86dB 16~86dB 16~86dB 20~60dB

Dynamic

Parameters APMC.2005[7] JSSC.2006[8] TCSI.2006[9]

Technology CMOS0.13um CMOS0.18um CMOS0.13

Standard UMTS

WLAN

WLAN WLAN

UMTS

Power supply 2.5V 1.6-2V 1.2

3-dB bandwidth 3.4~40MHz 2.1,11MHz

Power

Dynamic range 1.4%@ -8dB gain 52(1.4Vpp)

Table 13 Measurement comparison

Chapter 4

Conclusion

The thesis has presented an analog baseband circuit employing a linear-in dB

VGA and a tunable LPF for WiMax. It includes of three 14MHz low power VGA and a tunable bandwidth low power LPF. The novel topology has been applied to the analog front-end for WiMax direct conversion receiver which perform low power, wide dynamic gain range and high data rate. In conclusion, the key contributions presented in previous chapters are summarized below.

4.1 Summary

An optimum arrangement of LPF and VGA for noise figure and interference

trade-off is presented. Two transconductor operating in triode region for a tunable transconductor-C LPF is presented. A linear-in dB topology employing novel pseudo exponential technique for a low power VGA is presented. We use three VGA blocks and a LPF to constitute the analog baseband circuit. The analog baseband circuit

implemented in 0.13-

µ m CMOS process and arrange LPF in second location. The

circuit provides a minimum gain of 16dB and maximum gain of 86dB while drawing 26.8wW from a 1.2-V supply. The dynamic range is 38.19dB for 0.4Vpp. The measurement result of LPF is presented

4.2 Future Work

In the thesis, there are some design considerations which we didn’t attention. We give some recommendations and improvement in the section. First the analog baseband design is not optimum. The 2nd and 3rd VGA block gain range can be changed to have larger output swing for total design. The loading of each block didn’t consider comprehensively so the bandwidth was limited. Second the non-ideal resistor of each transconductor is considered too much so the pole and zero will shift from the ideal value and the frequency response will decrease in advance. The layout didn’t consider parasitic capacitors completely. Third the control circuit of the VGA block is only an inverter and DC shift circuit and the better choice is use OP to do control circuit. We didn’t consider best choice is using OP for control circuit. We will make an improvement in the future work.

Bibliography

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[3] Yodprasit, U.; Enz, C.C. “A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m” JSSC.2003.

[4] Po-Chiun Huang; Li-Yu Chiou; Chorng-Kuang Wang “A 3.3-V CMOS wideband exponential control variable-gain-amplifier;” ISCAS.1998.704417

[5] Chao-Chun Sung, Mei-Fen Chou and Kuei-Ann Wen, "Low Power CMOS Wideband Variable Gain Amplifier", Proc. IASTED Int. Conf. on Circuits, Signals, and Systems, Clearwater Beach, Florida, U.S.A., pp. 126-129, (November 2004).

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