1-1 Overview of Thin-Film Transistors (TFTs)
Thin-film field-effect transistors (TFTs) utilize the modulation of conductivity of a semiconductor film by the voltage of an insulated gate. In contrast with the metal-oxide
semiconductor field-effect transistor (MOSFET) the TFTs can be made using thin films of
either amorphous or polycrystalline semiconductors. As the TFTs do not require single crystal
semiconductor material, it can be fabricated on a variety of insulating substrates. The major
application for the TFTs at present is in active matrix flat panel displays (AMFPD). A circuit
diagram of an active matrix liquid crystal display is shown in Fig. 1-1. Each pixel consists of
a capacitor with liquid crystal material as the dielectric (CLC), storage capacitor (CS) and a
switching transistor. TFTs are turned on by applying a voltage to single row (scan line). Then,
the signal is transferred to the capacitor (pixel) from the data line. The liquid crystal material
rotates the polarization of light to a degree, which depends on the applied electric field. The
intensity of transmitted light is thus determined by the signal applied to the data line. When
the gate voltage is returned to zero, the signal remains on the capacitor for a time determined
2
by the leakage current (Ilk) of the TFTs. The leakage current should be low enough so
grayscale levels can be maintained over the frame refresh time.
Fig. 1-1
Circuit diagram of an active matrix liquid crystal display (AMLCD).Thin-film transistors is a fundamental component of AMFPD; therefore, to investigate the
TFTs is very important for the development of flat panel display technology.
3
1-1-1 Amorphous Silicon (α-Si) TFTs
Compare to the conventional cathode ray tube (CRT) display, the flat panel display has light
weight and small volume. Among many productive flat panel display, the active matrix liquid
crystal display (AMLCD) have widely use in many applications, such as laptop and desktop
monitor. Today, the α-Si TFT-LCDs have dominated the large area flat panel display market.
The TFT-LCDs have become the standard component of laptop, desktop monitor and digital
camera.
Active matrix liquid crystal display fabricated on α-Si TFTs is the most usual technique,
due to the advantages such as low temperature process (<350°C), [1.1,1.2] suitable for large
area, non-expensive glass substrate and lower leakage current, that is enabling for pixel
switching. Nevertheless, the α-Si TFTs exhibited poor field-effect carrier mobility (typically
µFE< 1 cm2/V-s) and smaller on current. This is due to the poor electrical performance of the
α-Si TFTs. To achieve the needed current flow for the grayscale of the frame, the dimension
of α-Si TFTs device was increased. Resolution of the display will be decreased resulted from
the large α-Si TFTs. The high-resolution TFT-LCD needs new solution to improve the mobility
of TFTs. The poly-Si TFTs technology is one of the potential methods to achieve the
requirement of high-resolution TFT LCD. And the poor field-effect carrier mobility can be
overcome easily using the poly-Si films as the active layer of the TFTs.
4
1-1-2 Low-Temperature Polycrystalline Silicon (LTPS) TFTs
In 1980, high temperature polycrystalline silicon TFTs had been introduced.[1.3] They
used chemical-vapor deposited poly-Si to achieve good carrier mobility and electrical
characteristics. With mobility around 50 cm2/V-s, these high temperature poly-Si TFTs were
employed gate insulator SiO2 grown thermally at 1050°C. This approach requires a high strain
temperature substrate such as quartz, incompatible with the commercially available large area
non-expensive glass substrate.
Recently, many researchers have developed various techniques for crystallization of α-Si at
low temperature (below 600°C), and then transformation it to poly-Si; the motivation for
pushing up the mobility to be able to integrate drive circuitry [1.4,1.5] as well as providing
pixel TFTs and more compatible with the glass substrate. In fact, the field effect mobility of
poly-Si TFTs is significantly higher than that of α-Si about two orders of magnitudes. The
higher drive current allows small TFTs dimension to be used as the pixel switching elements,
resulting in higher aperture ratio and lower parasitic gate-line capacitance for improved
display performance. [1.6]
Unlike MOSFETs, where the active layer is part of the substrate, in the case of TFTs the
active layer needs to be separately formed on the host substrate. The crystallization method
affect the microstructure quality of the resulting poly-Si film, which means that the
performance of poly-Si TFT will be affected by the selection of techniques for the
5 crystallization of Si films.
A various techniques have been investigated for crystallization of α-Si at low temperature
such as: (1) solid phase crystallization (SPC) (2) excimer laser Annealing (ELA) (3) Ni-metal
induced/Ni-metal induced lateral crystallization (NIC/NILC). In the following section, we
will review the crystallization method that the above-mentioned.
6
1-2 Low-Temperature Polycrystalline Silicon (LTPS) Crystallization Method
Crystallization of α-Si films has been considered as the most important process step in the
fabrication of LTPS TFTs. The quality of crystallized poly-Si films is quite sensitive to the
performance of poly-Si TFT. In poly-Si films, most defects are generated at the grain
boundaries. Enlarging the grain size can promote the quality of poly-Si, as deposited poly-Si
generally exhibits small grain size. In general, the poly-Si crystallized from α-Si usually has
larger grain size than that of as-deposited poly-Si. Historically, solid phase crystallization [1.7]
was the first technology to produce poly-Si films for display applications, followed by laser
crystallization. The ultimate goal of the LTPS technology is to integrate the pixel-driving
circuits on the display substrate. Fig. 1-2 shows the anticipated evolution of poly-Si
technology development and its impact on the degree of on-panel integration.[1.8]
Fig. 1-2
Roadmap of poly-Si TFT technology.7
1-2-1 Solid Phase Crystallization (SPC) Method
Deposited α-Si thin films were transformed to poly-Si using SPC method has obtained
better TFT device electrical performance [1.9] than as-deposited poly-Si films. For the SPC
method, α-Si films are crystallized in a furnace at temperature about 600°C for duration time
(about 24 h). The polycrystalline grains are generally in oval-shaped, and large defect density
exists in poly-Si films. Amorphous Si is a thermodynamically meta-stable phase possessing a
driving force for transformation to polycrystalline phase given a sufficient energy to
overcome the initial energy barrier.
A key factor affecting crystallization is the nucleation rate in the α-Si films. The nucleation
rate is strongly influenced by the selected deposition method and condition. [1.10,1.11] The
structural order/disorder in the α-Si films affects the films to form stable nuclei. Higher
disorder structure increases the energy barrier required to form the Si nuclei; this concept has
been used in the past to increase the grain size of poly-Si films. Ideally, a small number of
fast-growing nuclei are needed to maximize the grain size. However, the reality of the
situation is that the probability that additional nucleation events will occur within the volume
separating growing nuclei increases geometrically with the separation distance.
8
1200°C. However, only sustained for a very short time; therefore, it will not damage the glass
substrate. Moreover, as shown in Fig. 1-3, there are two major transformation regimes
(occurring at low and high laser energy, respectively) and one minor transformation regime in
between (that so-called superlateral growth, or SLG).[1.12,1.13] The low laser energy regime
describes a situation where the incident laser is sufficient to induce melting of the silicon
films, but it is low enough that a continuous layer of silicon at the maximum extent of melting.
For this reason, this regime is referred to as the partial melting regime. The high laser energy
regime corresponds to a situation that the laser energy is sufficiently high to completely melt
the silicon film; this regime is also referred to as complete melting regime. In addition to
these two regimes, a third regime has been found to exist within a very narrow experimental
window in between the two main regimes. Despite the small extent of this region, it is
nonetheless one with great technological significance, because the poly-Si films within the
regime feature large-grained polycrystalline microstructures.[1.14] The stable grain size of
ELA poly-Si films is typically limited to 0.3~0.6 µm. Larger grain size is possible within the
9
SLG window, but this regime is intrinsically unstable.
Fig. 1-3
Illustration of transformation scenarios during the ELA process. Correspond to (a) partial melting, (b) completely melting and (c) near-completely melting of theinitial Si film.
The surface roughness in ELA poly-Si films is localized at the planes and point of
congruence of grain boundaries. The mechanism for the formation of roughness is well
understood and is attributed to the specific density difference between molten Si (2.53 g cm-3)
and solid Si (2.30 g cm-3). In other words, as the molten Si solidifies, it simultaneously
expands. Solidification starts from neighboring seed areas, and the last region to solidify is the
volume at the vicinity of the two colliding lateral fronts. As that happens, the generated solid
Si can only expand upward, as shown in Fig. 1-4, thus generating the ridge associated with
the formation of the grain boundary at the location.
10
Fig. 1-4
Solidification of the molten Si film. Resulting in the higher surface roughness.Although the highest quality poly-Si films were fabricated by ELA method, the poor grain
size uniformity and high roughness ELA poly-Si films degraded the performance of
TFT.[1.15]
1-2-3 Ni-Metal Induced Crystallization (NIC) / Ni-Metal Induced Lateral Crystallization (NILC) Method
Solid phase crystallization of α-Si needed a high temperature and longer annealing time for
furnace annealing process. In the NIC/NILC method,[1.16~1.19] the annealing time and
temperature could be reduced, and the grain size of NILC poly-Si films uniformly over large
area could be obtained. In 2000, Sharp Corp. and SEL (Semiconductor Energy Lab.) propose
the CGSi (Continuous Grain Silicon) technique to fabricate the 60 inch HDTV rear
11
projector.[1.20] When thin Ni is deposited on α-Si and annealed, Ni disilicide (NiSi2)
forms.[1.21] The nickel disilicide is cubic with CaF2 structure and has a very close lattice
parameter match to c-Si (-0.4%), the lattice constant of NiSi2, 5.406A, is nearly equal to that
of Si, 5.430A. The disilicide is actually the species that mediates the transformation of α-Si to
c-Si. As shown in Fig. 1-5, the c-Si formed below the Ni-pad is called NIC and the lateral
growth is called NILC.
Fig. 1-5
Schematic illustration of the Ni-metal induced Crystallization (NIC) and Ni-metal induced lateral crystallization (NILC).The silicide mediate growth of silicon occurs in three stages. In the first stage, precipitation
and growth of NiSi2 occur in the temperature range of 325~400°C. In the second phase,
crystalline Si nucleates on one or more the eight {111} faces of the octahedral NiSi2, as
shown in Fig. 1-6. Finally, in the third phase, c-Si growth proceeds with a NiSi2 precipitate at
the planar advancing growth front.
12
As shown in Fig. 1-6, for <110>-oriented precipitates, four of the {111} planes exhibit
surface normal within the planes of the film, which makes extensive growth possible. On the
other hand, the <100>- and <111>-oriented precipitates exhibits {111} planes normal that
intersect the upper and lower surface of α-Si films.
Fig. 1-6
Schematic representation of favorable precipitate orientations for long-range growth of epitaxial Si within the plane of the α-Si.
The driving force for the migration of NiSi2 precipitates is reduction in the free energy
associated with the transformation of meta-stable α-Si to stable c-Si. An equilibrium
free-energy diagram is provided for explanation, as shown in Fig. 1-7.[1.21] It is well known
that the α-Si has a higher free energy than c-Si. In the case of Ni silicide mediated
crystallization, the free energy difference between Ni and Si atoms at the NiSi2/α-Si and
NiSi2/c-Si interface acts as the driving force for Ni diffusion.[1.21] The free energy of the Ni
atom is lower at the NiSi2/α-Si interface than at the NiSi2/c-Si interface, whereas the free
13
energy of the Si atom is lower at the NiSi2/c-Si interface. Therefore, with the dissociative
model,[1.21] the NiSi2 layer dissociates to provide free Si for epitaxial growth of c-Si at the
c-Si/NiSi2 interface by the diffusion of Ni atoms. The Ni atoms diffuse to α-Si following by
formation of a fresh NiSi2/α-Si interface. Repetition of this process results in migration of
NiSi2 precipitates through α-Si and growth of needlelike Si. Fig. 1-8 shows a schematic
representation of a possible growth process incorporating the formation of intermediate thin
layer of c-Si on the leading edge of migrating NiSi2 precipitate.[1.21] As a result of this
growth mechanism, NILC poly-Si films demonstrate a needlelike microstructure, with each
needle grain attribute to c-Si growth from an individual disilicide precipitate.
Fig. 1-7
Schematic equilibrium molar free-energy diagram for NiSi2 in contact with α-Si.In addition to Ni, other metals have been investigated as far as their effectiveness in
14
enhancing Si crystal growth. These include Au[1.22], Al[1.23] and Sb[1.24] which form
eutectic with Si, and Pd[1.25,1.26], which form silicide with Si.
Fig. 1-8
Schematic representation of a possible growth mechanism involoving the formation of a thin layer of c-Si at the NiSi2/α-Si interface.15
As a result, Ni remains the undisputed metal of choice for silicide-assisted crystallization. It
should be noted that traces of NiSi2 also remain within the c-Si that is left behind after the
growth phase. This would have presented an insurmountable obstacle had it not been for the
existence of an efficient gettering process.[1.27,1.28] This process utilizes the implantation of
phosphorous, followed by low-temperature annealing to generate electrically inactive
compounds. Previous studies have demonstrated the effectiveness of the gettering process in
removing the remaining silicide in the film after Si crystallization.[1.20,1.29] In practice,
the necessity to maintain a low processing temperature poses certain limitations on the quality
of the poly-Si microstructure. One way to boost the poly-Si quality is by combining NILC
with laser annealing process [1.30,1.31] to produce high quality and good uniformity poly-Si
films to realize the system-on-panel technology.[1.8,1.32-1.33]
In this thesis, we will focus on the Ni-metal induced lateral crystallization method. To
discuss the growth mechanism of NILC and utilized Ni-metal imprint induced crystallization
method[1.34] to fabricate the LTPS TFT. Moreover, to produce high performance LTPS
TFTs by combined Ni-metal imprint and ELA method. And develop a simple method to
getter the nickel impurity within the NILC polycrystalline silicon films.
16
1-3 Electrical Characteristics of Ni-Metal Induced Lateral Crystallization (NILC) Thin Film Transistors
The NILC method has some advantages over other crystallization methods such as: lower
equipment cost, better uniformity than ELA method, and lower thermal budget than SPC
method. However, several intrinsic growth characteristics of NILC method always resulted in
poor TFT performance, such as higher leakage current (Ilk) and poor electrical stability due to
large defect (trap state) density in NIC/NILC interface and NILC/NILC grain boundary and
high Ni metal contamination.[1.35~1.39] Fig. 1-9 illustrates the leakage current model using
band diagrams,[1.40-1.42] the first situation in Fig. 1-9 (a) is described only the thermal
activation of an electron from the valence band to the conduction band. The second situation
in Fig. 1-9 (b), the leakage current is induced by the trap or surface state in the band gap. With
increase the drain bias, the activation energy of leakage current decreases, which suggests that
the high field in the drain depletion region has reduced the barrier that the electron must
overcome. This situation comprises two steps: the first step is the thermal activation of an
electron from the valence band to a trap state (Et) in the band gap, and the second step is
electron tunneling through this reduced barrier to the conduction band. As such, the dominant
leakage current mechanism is thermionic field emission. The third situation in Fig. 1-9 (c) is
induced under strong electric field, in which the dominant leakage current mechanism is pure
tunneling. With the increase of the electric field, the tunneling length decreases. The presence
17
of the trap state in the band gap assists the process by shorting the effective tunneling length
of the electron. In addition, the trap state in the band gap plays an important role in the
leakage current model. In the traditional MOSFET, those situations do not occur easily
because the trap state is low. This causes different leakage current between MOSFET and
TFTs.
Moreover, the Ni contamination of the NILC poly-Si films can degrade the minority carrier
life time and increase the leakage current. The leakage current is proportional to the impurity
concentration. [1.43,1.44]
In order to solve the above problems, the post-annealing treatment [1.30,1.45-1.47] was
Fig. 1-9
The band diagram for the leakage current model. (a) Case of weak electric field. (b) Case of medium electric field. (c) Case of strong electric field.18
proposed to reduce the NILC/NILC grain boundary defect density. Moreover, gettering
process [1.20,1.29] was proposed to reduce the Ni-metal contamination within the NILC
poly-Si films. In the following, we will discuss the effects of grain boundary and Ni-metal
impurity on the electrical performance of NILC TFTs.
19
1-4 Motivation and Thesis Organization
In this thesis, the major research subject is Ni-metal induced lateral crystallization of
amorphous silicon, which involved of the tensile stress effects on the NILC growth
mechanism. It has been reported that the Ni-metal imprint method introduced a tensile stress,
while the crystallization process and the incubation time could be reduced by tensile stress.
However, the detail of the tensile stress effects on the growth mechanism of NILC has still
not been clarified. In addition, in this study, we chose the Ni-metal imprint-induced
crystallization method due to it exhibited many superior characteristics over traditional NILC
method, such as: higher growth rate, better crystallization quality and less branch needle-like
grain microstructure. But, between the NILC/NILC needle-like gains contained many
un-crystallized region; these intra-grain defects can degrade the device performance.
Therefore, combine NILC and ELA method to gather the advantages of each method,
producing the high performance TFTs device. Finally, the most important issue for the NILC
poly-Si film is the Ni-impurity contamination. To develop a simple gettering method for
reduced the Ni-impurity within the NILC poly-Si films.
In chapter 2, the influence of tensile stress on the growth of NILC of α-Si was investigated
by using a simple bending fixture. Before the growth of needlelike poly-Si grains, there must
be an incubation period, which included (1) the formation of NiSi2 and (2) the nucleation of
c-Si on NiSi2. It has been reported that the incubation time could be reduced by tensile stress.
20
TFTs device. For traditional NILC method, Crystalline Si nucleates on {111} faces of NiSi2.
The crystallization of needlelike Si grains proceeds via the migration of nickel silicides
through α-Si. The orientation of needle grain is <111>. Unfortunately, the NILC poly-Si film
has intra-grain defects and some un-crystallized regions between poly-Si grains. In this
chapter, these defects were reduced by Ni-metal imprint induced crystallization method. In
Ni-metal imprint method, a thin Ni metal layer was deposited on the imprint mold. The mold
and α-Si film were then pressed together and annealed at 550°C. The orientation of Ni-metal
imprint needle grains is <112>, which differed from that of NILC needle grains <111>.
Therefore, the principal goal of this chapter has been to investigate the performances of TFTs
Therefore, the principal goal of this chapter has been to investigate the performances of TFTs