4-1 The Conception of the Post Laser Treatment
The improved performance and good uniformity LTPS TFTs have been fabricated using
NILC method. However, the polycrystalline silicon film are existed many NILC/NILC
intra-grain defects with some un-crystallized regions between poly-Si needle grains. These
defects degrade the transfer characteristics of TFT devices, including the field effect mobility
(µFE) and the leakage current.[4.1-4.5] As mentioned in chapter 3, the Ni-metal imprint
induced crystallization method [4.6-4.8] has many better characteristics than the traditional
NILC method, including fewer branch grains and a higher grain growth rate. However, some
α-Si regions are present between needle grains. As a result, in order to reduce the defect
density in the poly-Si, another post annealing process seems to be required.
A high temperature (>900°C) annealing [4.9] using conventional furnace seems not
compatible with low strain temperature glass substrate. As mentioned in chapter 1, the
excellent electrical characteristic LTPS TFTs fabricated using ELA method suffer from poor
uniformity of device performance. This is due to the narrow process window of laser
64 annealing.
Obviously, a high quality poly-Si films with large grains can be produced by a combination
of NILC and ELA method. To gather the advantages of both crystallization methods produced
high performance and good uniformity LTPS TFTs. In this study, the NILC poly-Si films was
crystallized using Ni-metal imprint induced crystallization method, followed by excimer laser
annealing to reduce the defect density.
(2) “IMPRINT-ELA” utilized the same imprint method with an additional ELA process. The
imprint process is shown in Fig. 4-1 (a).
P-type (100) silicon wafers were used to fabricate imprint mold and α-Si/SiO2/Si wafer.
The imprint mold was prepared by wet chemical etching using potassium hydroxide (45wt %)
solution at 70°C, the same process has been described in chapter 3. Figure 4-1(b) shows the
SEM image of an imprint mold. A 2-nm-thick Ni was then deposited on the imprint mold by
sputtering. As for theα-Si/SiO2/Si, a 500 nm-thick wet thermal oxide layer was grown on the
65
Si wafer, and then a 100 nm silane-based α-Si film was deposited using a low-pressure
chemical vapor deposition (LPCVD) system. The deposition pressure and temperature were
100 mTorr and 550°C, respectively.
Fig. 4-1
(a) The Schematic illustration of Ni-imprint method. (b) SEM image of imprint mold.66
Imprint mold and α-Si/SiO2 /Si wafer were pressed in a differential thermal expansion
coefficient apparatus, made of stainless steel, molybdenum and highly pure graphite.[4.10] To
fabricate the IMPRINT poly-Si, the sample stack was first clamped at room temperature and a
minimal compressive load was applied; it was then annealed at 550°C for 24 h. After the
sample stack was separated, as shown in Fig. 4-2, the IMPRINT poly-Si films were irradiated
by a KrF excimer laser (Lambda Physik LPX-210i, λ~248 nm) at room temperature with the
N2 flow rate of 50 sccm at a pressure of 800 mtorr to fabricate the IMPRINT-ELA poly-Si
films. The laser beam spot size of 1.8×23.1 mm was scanned with a 95% overlap from pulse
to pulse and its repetition rate was maintained at 20 Hz. The principle setup of excimer laser
crystallization system is shown in Fig. 4-3.
Fig. 4-2
Illustration of the Ni-metal imprint poly-Si with post excimer laser treatment process.67
Fig. 4-3
Setup of excimer laser annealing system.4-2-2 Fabrication of the IMPRINT-ELA TFTs
As shown in Fig. 4-4, TFTs were fabricated by patterning the Si islands as active areas on
the IMPRINT and IMPRINT-ELA poly-Si films. A 100nm-thick tetraethylorthosilicate/O2
oxide layer was deposited as the gate insulator by plasma-enhanced chemical vapor
deposition (PECVD). Then, a 150nm-thick poly-Si film was deposited for gate electrodes by
high-density plasma chemical vapor deposition (HDP-CVD) at 350°C. After defining the gate,
self-aligned 35keV phosphorus ions were implanted at a dose of 5×1015 ions/cm2 to form the
source/drain and gate. The implanted dopants were activated by thermal annealing at 600°C
68
for 24h. A 500nm-thick SiO2 film was deposited by PECVD to serve as a passivation layer.
Contact holes were opened through the oxide layer, and 500nm of aluminum (Al) was
deposited as the interconnection. In this study, the device characteristics were all intrinsic,
without any hydrogen plasma treatment.
Fig. 4-4
Flow chart of TFT device fabrication process.69
4-3 Results and Discussion
4-3-1 Microstructure Analysis of Polycrystalline Films
Figure 4-5 (a) shows an SEM image of the Secco-etched IMPRINT poly-Si grains.
Fig. 4-5
(a) The SEM image of Secco-etched Ni-imprint poly-Si film. The needle grains were parallel to each other. (b) The TEM image and the correspondingdiffraction pattern of the Ni-imprint poly-Si.
Most of the grains were parallel to each other. Only few branch grains were observed. The
width of the needlelike grains was around 50nm. Among these grains remained some
un-crystallized α-Si regions, which had been etched away. The TEM bright field image and
70
the diffraction pattern of the Ni-imprint Si grains are shown in Fig. 4-5 (b). It reveals the
IMPRINT grains with <111> orientation (perpendicular to the substrate).
This result was the same as that of other imprint methods.[4.7-4.8] This orientation,
however, was different from that of conventional NILC poly-Si orientation, <110>.[4.11] The
diffraction pattern also reveals that the growth direction of the needlelike IMPRINT grains
was along the <112>, which differed from that of conventional NILC Si grains, <111>.[4.11]
These difference between the orientations of the needlelike grains influenced the growth of
poly-Si; it might be the reason why only a few branch grains were found in IMPRINT films.
To fabricate IMPRINT-ELA poly-Si films, IMPRINT films were then irradiated using an
excimer laser. The scan direction of the laser was parallel to the crystallization direction of
needlelike poly-Si grains, <112>, as illustrated in Fig. 4-5. The laser energy density varied
from 225 to 430 mJ/cm2. The grain size as a function of laser energy density is shown in Fig.
4-6 (a). As the laser energy reached 345 mJ/cm2, the width of the grains increased markedly
from 50nm to 250nm, as presented in Fig. 4-6 (b). Similar results have been reported by Hu et
al.[4.12] who converted an α-Si film to poly-Si using NILC method. After the NILC poly-Si
film was annealed using an excimer laser (ELA), they found that most of the α-Si and small
Si grains were molten when the laser energy was between 230mJ/cm2 and 265mJ/cm2.
However, the large grains were only molten partially and served as the nuclei for
predetermined to grow. The width of these grains markedly increased to 600nm due to the
71
geometrical coalescence of Si needle grains. Geometrical coalescence can be simply
described as an encounter of grains whose relative orientations are similar during the grain
growth. The grain boundary between grains disappears, resulting in the sudden development
of a much larger grain.[4.13] This coalescence is an important phenomenon for grains having
a strong preferred orientation. Since our IMPRINT needlelike grains had a strong preferred
orientation <112>, it was favorable for the geometrical coalescence to occur.
72
Fig. 4-6
(a) Grain size versus laser energy density. (b) The SEM image of Secco-etched IMPRINT-ELA poly-Si film.However, the IMPRINT-ELA sample herein has smaller grains than the geometrically
coalesced sample of Hu et al., and requires a higher laser energy density. We believe that
73
these variations are caused mainly by the differences between the film thicknesses and the
preferred orientations of the needle grains. In this case, the film thickness of the
IMPRINT-ELA sample was 100 nm, which exceeded that of the NILC-ELA sample (50 nm)
of Hu et al. The preferred orientation of the needle grains of the IMPRINT-ELA film was
along <112>, whereas that in the NILC-ELA film was along <111>.
4-3-2 Electrical Characteristic of IMPRINT and IMPRINT-ELA TFTs
The performance of TFT devices was also used to examine the quality of poly-Si films, as
shown in Fig. 4-7 and Table I. The subthreshold slope and field effect mobility was extracted
from the maximum transconductance in the linear region at a drain bias (VDS)of 0.1 V. The
ION/IOFF current ratio was defined at VDS = 5 V. It was found that the field effect electron
mobility (µFE) of the IMPRINT-ELA-TFT was 413 cm2/V-s, which was 31.7 times higher
than that of the IMPRINT-TFT. The ION/IOFF current ratio of the IMPRINT-ELA-TFT was
4.24×106, which was greater by two orders of magnitude than that of the IMPRINT-TFT. The
threshold voltage of IMPRINT-ELA-TFT was 0.848 V, which was less than that of the
IMPRINT-TFT, 1.9 V.
As mentioned earlier, some α-Si regions remained among the IMPRINT poly-Si grains.
These regions (boundaries) trap charge carriers and constitute potential barriers to the flow of
74
carriers. The presence of the potential barriers and the additional scattering at the boundaries
degrade the mobility.[4.4]
Fig. 4-7
The Transfer characteristics of IMPRINT-TFT and IMPRINT-ELA-TFT with a laser energy density of 345 mJ/cm2.IMPRINT-ELA-TFTs do not have these problems because, as presented in Fig. 3(b), most
of the geometrical coalescence grains and their boundaries are parallel to the drain current
(IDS), reducing the impedance to carrier flow and, thereby, reducing the threshold voltage and
greatly increasing the mobility. The higher ION/IOFF current ratio of the IMPRINT-ELA-TFT
than the IMPRINT-TFT was also attributed to the larger grains and the fewer intra-grain
75
defects. However, this geometrical coalescence grain growth resulted in a significant increase
in surface roughness. The root mean square surface (rms) roughness of IMPRINT-ELA
surface (4.334 nm) was much greater than that of IMPRINT surface (0.544 nm). Since the
subthreshold slope increased with the surface roughness,[4.14] the subthreshold slope of
IMPRINT-ELA-TFT was higher than that of IMPRINT-TFT.
Table I
Summary of device characteristics of IMPRINT-TFT and IMPRINT-ELA-TFT with a laser energy density of 345 mJ/cm2.
The existence of grain boundaries and intra-grain trap states are also responsible for the
increase in leakage current of TFTs. At high VDS, the leakage current is dominated by trap
sites-associated field emission current.[4.15,4.16] As shown in Fig. 4, at VGS= -10V and VDS=
5V, the leakage current of the IMPRINT-TFT approaches 10-8A, which is 100 times greater
76
than that of the IMPRINT-ELA-TFT. The leakage current of the IMPRINT-ELA-TFT is less
sensitive to the gate voltage because the density of defect state is lower than that of the
IMPRINT-ELA-TFT, the channel resistance was reduced resulting in the increase in leakage
current.[4.3]
4-4 Summary
High-performance LTPS TFT fabricated by IMPRINT-ELA was investigated. In this
process, amorphous silicon was first transformed to poly-Si using a Ni-imprint method at
550°C for 24 h, and then annealed using a KrF excimer laser. Most IMPRINT Si grains were
parallel to each other. The preferred orientation of needle grains (parallel to the film) was
<112>, which differed from that of the conventional NILC Si grains <111>. Laser annealing
at an energy density of 345 mJ/cm2 greatly increased the width of the needle grains from
50nm to 250nm by geometrical coalescence. IMPRINT-ELA-TFT markedly outperformed the
IMPRINT-TFT because the IMPRINT-ELA poly-Si film had larger grains and fewer
77
intra-grain defects than the IMPRINT poly-Si film. The IMPRINT-ELA-TFT has a lower
threshold voltage, and a higher ION/IOFF current ratio than the IMPRINT-TFT. The mobility of
IMPRINT-ELA-TFT was 413 cm2/V-s, which was 31.7 times higher than that of the
IMPRINT-TFT. The on/off current ratio of the IMPRINT-ELA-TFT was 4.24×106, which
was higher by two orders magnitude than that of the IMPRINT-TFT.
78
Reference:
[4.1] M. Wong, Z. Jin, G. A. Bhat, P. C. Wong, and H. S. Kwok, “Characterization of the
MIC/MILC interface and its effects on the performance of MILC thin-film transistors.”
IEEE Trans. Electron Device, vol. 47, pp. 1061-1067, 2000.
[4.2] G. A. Bhat, H. S. Kwok, and M. Wong, “Behavior of the drain leakage current in
metal-induced laterally crystallization thin film transistors.” Solid-State Electronics, vol.
44, pp. 1321-1324, 2000.
[4.3] G. Bhat, H. Kwok, and M. Wong, “Plasma hydrogenation of metal-induced laterally
crystallized thin film transistors.” IEEE Electron Device Lett., vol. 21, pp. 73-75, 2000.
[4.4] G. A. Bhat, Z. Jin, H. S. Kwok, and M. Wong, “Effects of longitudinal grain boundaries
on the performance of MILC-TFT’s.” IEEE Electron Device Lett., vol. 20, pp. 97-99,
1999.
[4.5] T- K Kim, G- B Kim, B-I Lee, and S-K Joo,”The effects of electrical stress and
temperature on the properties of polycrystalline silicon thin-film transistors fabricated
by metal induced lateral crystallization.” IEEE Electron Device Lett., vol. 21, pp.
347-349, 2000.
[4.6] K. Makihira, and T. Asano, “Enhanced nucleation in solid-phase crystallization of
amorphous Si by imprint technology.” Appl. Phys. Lett., vol. 76, pp. 3774-3776, 2000.
[4.7] K. Makihira, M. Yoshii, and T. Asano, “CMOS Application of Single-Grain Thin Film
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Transistor Produced Using Metal Imprint Technology.” Jpn. J. Appl. Phys. Lett., vol. 42,
pp. 1983-1987, 2003.
[4.8] K. H. Kim, S. J. Park, K. S. Cho, J. H. Oh, W. S. Sohn, J. U. Kwak, S. H. Kang, Y. D.
Son, and J. Jang, “Controlling Nucleation Sites for Silicide-Mediated Crystallization
of Amorphous Silicon.” Society Information Display Digest, pp. 1306-1309, 2003.
[4.9] M. Wang, Z. Meng, and M. Wong, “The Effects of High Temperature Annealing on
Metal-Induced Laterally Crystallized Polycrystalline Silicon.” IEEE Trans. Electron
Device, vol. 47, pp. 2061-2067, 2000.
[4.10] P. C. Liu, C. Y. Hou, and Y. S. Wu, ”Wafer bonding for high-brightness light-emitting
diodes via indium tin oxide intermediate layers.” Thin Solid Films vol. 478, pp.
280-285, 2005.
[4.11] S. Y. Yoon, S. J. Park, K. H. Kim, and J. Jang, “Metal-induced crystallization of
amorphous silicon.” Thin Solid Films, vol. 383, pp. 34-38, 2001.
[4.12] G. R. Hu, Y. S. Wu, C. W. Chao, and H. C. Shih, “Growth mechanism of laser
annealing of Nickel-induced lateral crystallization silicon films.” Jpn. J. Appl. Phys.,
vol. 45, pp. 21-27, 2006.
[4.13] Robert E., Reed-Hill and R. Abbaschian, Physical Metallurgy Principles, p. 254,
Thomson, Boston ,1992.
[4.14] K. C. Park, J. H. Lee, I. H. Song, S. H. Jung and M. K. Han, “Poly-Si thin film
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transistors fabricated by combining excimer laser annealing and metal induced lateral
crystallization.” J. of Non-Cryst. Solids, vol. 299-302, pp. 1330-1334, 2002.
[4.15] K. R. Olasupo, and M. K. Hatalis, “Leakage current mechanism in sub-micro
polysilicon thin film transistors.” IEEE Trans. Electron Device, vol. 43, pp. 1218-1223,
1996.
[4.16] M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction mechanism of leakage current
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81
Chapter 5 Gettering of Nickel from NILC Polycrystalline Silicon Films
5-1 The Conception of the Gettering Method
Transition metals (e.g. Ni, Cu, Pd…..) are common impurities in silicon originating from
the crystal growth and subsequently integrated circuits (IC) fabrication steps. The metal
contamination can degrade the minority carrier lifetime and device performance, and increase
the junction leakage current.[5.1-5.3]
Gettering is defined as the process of removing device-degrading impurities from the
active layer regions, which is an important ingredient for enhancing the performance and the
yield of device manufacturing. In general, the mechanism by which gettering removes
impurities from device regions may be described by the following steps: (1) the impurities to
be gettered are released into solid solution from whatever precipitate they're in; (2) they
undergo diffusion through the silicon; (3) they are trapped by defects such as dislocations or
precipitates in an area away from device regions.
There are two general classifications of gettering, namely, extrinsic, and intrinsic.
Extrinsic gettering refers to gettering that employs external means to create the damage or
82
stress in the silicon lattice in such a way that extended defects needed for trapping impurities
are formed. These chemically reactive trapping sites are usually located at the wafer
backside.
Several methods have been used to accomplish external gettering. For instance, the
introduction of mechanical damage by abrasion, grooving, or sandblasting can produce
stresses at the backside of a wafer, which when annealed create dislocations that tend to
relieve these stresses. These locations can then serve as gettering sites. The main drawback
of this method, of course, is its tendency to initiate and propagate wafer backside
microcracks that may compromise the mechanical strength of the wafer.
Diffusing phosphorus [5.4,5.5] into the wafer backside is another technique used for
external gettering. Phosphorus diffusion into silicon results in phosphorus vacancies or
dislocations that serve as trapping sites for impurity atoms, such as gold. Another effect of
P diffusion is the creation of Si-P precipitates, which have been shown to be capable of
removing Ni impurities through interactions between Si self-interstitials and Ni atoms,
nucleating NiSi2 particles in the process.
Introduction of damage by laser is another external gettering method.[5.8-5.10] Scanning
a laser beam across the wafer surface induce damage that is very similar to mechanical
damage, with the exception that the laser damage is “cleaner”. Laser subjects the irradiated
areas to thermal shock, forming dislocation nests that serve as gettering sites.
83
Ion bombardment to produce wafer backside damage is another method for external
gettering, [5.11-5.13] this time using high-energy ions to induce the necessary stress within
the lattices of the wafer backside. Deposition of a poly-Si layer on the wafer backside has
also been used for external gettering. Poly-Si layers introduce grain boundaries and lattice
disorder that can act as traps for mobile impurities.
Intrinsic gettering refers to gettering that involves impurity trapping sites created by
precipitating supersaturated oxygen out of the silicon wafer.[5.14-5.16] The precipitation
of supersaturated oxygen creates clusters that continuously grow, introducing stress to the
wafer as this happens.
As mentioned previously, the method of ion implantation to produce nano cavities as a
gettering site is too complicate and needed high temperature annealing (>900°C) which not
suited to the LTPS TFTs manufacturing process. For the method of diffusion of P atoms into
silicon region, the phosphorous will also contaminate the active region.
84
5-2 Gettering of Nickel within the NILC Polycrystalline Silicon Films Using α-Si Films
5-2-1 Introduction
In this study, we have used an α-Si layer as the gettering material and a silicon-nitride
(SiNx) layer as the diffusion and etching stop layer to accomplish the gettering process.
Using the α-Si as the gettering material in order to prevent the other elements contamination
and relied on the concentration gradient acts as a driving force for transport of Ni through
the SiNx to the α-Si, it is more compatible for the poly-Si TFTs fabrication and large area
application.
5-2-2 Experimental Procedure
Two types of poly-Si films were investigated in this study. Samples were designated as
follows: (1) “NILC poly-Si” was a poly-Si film fabricated with traditional NILC methods,
while (2) “GETR poly-Si" utilized the same traditional NILC method with an additional
Ni-gettering process.
Figure 5-1 shows the basic NILC fabrication process of both poly-Si films began with
four-inch Si (100) wafer substrates where wet thermal oxide films of 500nm were grown
85
using a H2/O2 mixture and substrate temperature of 1050°C. Silane-based α-Si films with
thicknesses of 100 nm were deposited using low-pressure chemical vapor deposition (LPCVD)
at 550°C and 100 mTorr. The photoresist was patterned to form the desired Ni lines, and a
2-nm-thick Ni film was deposited on the α-Si using an e-gun. Afterward, samples were
dipped into acetone and ultrasonic bath for 5 min to remove the photoresist. The samples were
subsequently annealed at 550°C for 24 h to form the NILC poly-Si film. Then, to form islands
of poly-Si regions on the wafers using photolithography process and reactive-ion etch (RIE)
system.
Fig. 5-1
Schematic illustration of basic NILC fabrication process of both poly-Si films. (a) is the α-Si / SiO2. (b) is the 2 nm Ni thin film deposited on the top of α-Si. (c) is theα-Si coated with Ni pads to form the NILC poly-Si. (d) is the NILC poly-Si
islands.
86
To form the GETR poly-Si film, a 30 nm SiNx layer was capped on the top of NILC
poly-Si film, and then 100-nm-thick α-Si was deposited on the top of SiNx film, as shown in
Fig. 5-2.