Ea Activation energy
ET Trap energy
EF Fermi level
F Electrical field in nitride
Ie Electron stress current
Ih Hole stress current
Id Drain current
L Channel length
me Electron effective mass in SiO2
N P/E cycle number
Nox Oxide trap density
Nt Trap density in top oxide
ne Electron concentration in the channel right below the trap nt Trapped charge density in silicon nitride
Qs Stored charge in the HfO2 dot
Qox Negative trapped charge in the bottom oxide
T Absolute temperature
t Measurement time
tox The oxide thickness
Vt Threshold voltage
Vg, Vd, Vs Gate, drain, and source voltage Vts Channel potential at the trap position
W Channel width
x Distance between a HfO2 trap and a top oxide trap
xt Distance of the trap from drain edge
αox Coefficient of tunneling probability through SiO2
ΔId RTN amplitude
ΔVt Program window
Δφs Local potential change at the trap position εox Dielectric constant of SiO2
φb Barrier height between the SiO2 and Si3N4 for electrons σ RTN amplitude distribution standard deviation
σt Trap cross section
τe, τc Electron emission time and capture time
τe(FP), τc(FP) Frenkel-Poole emission time and capture times
τeff Effective time for nitride trapped charge at the emission front to escape from the ONO film
τox Oxide tunneling time
υth Thermal velocity
<τc>,<τe> Average time of the capture time and emission tim
Chapter 1 Introduction
1.1 Backgrounds
In order to maintain the scaling roadmap, high permittivity (high-k) material is introduced to replace SiO2 to solve the gate leakage problem. Bias temperature stress induced current instability in SiO2 and high-k based gate dielectric CMOS was reported to be mainly issue on DC performance [1.1]-[1.8]. With the shrinkage of device dimension to atomic levels, variation between devices occurred due to the effects such as random dopant fluctuation [1.9]-[1.15]. Similarly, the effect of a single charge induced current fluctuation on a typical device can be quite significant.. In ultra small area device, the trapping of even a single carrier will potentially cause functional errors in digital logic circuits and memories. The effect of few carriers trapping has also become a major reliability issue in bulk MOSFETs. MOSFET degradation associated to trapping of carriers in stress-generated defects in the gate dielectric has become a matter of growing concern [1.16]-[1-21]. Fig. 1.1 illustrates multiple carriers were detrapping in negative bias stressed device [1-22]
Flash memory is a non-volatile computer data storage technology that can be electrically programmed, erased and read for many times and won’t be lost after cutting off the power. It is primarily used in memory cards, USB flash drives, and solid-state drives for general storage and transfer of data between computers and other digital products. With respect to charge storage devices, two state-of-art techniques attract great attention. (a) Floating gate (FG) devices: charge is stored in a thin conducting or semiconductor layer. (b) Charge trapping devices: Charge is stored in the traps at the interface and bulk of insulator, such as SONOS
device [1.23]. With the advanced VLSI processing, the effect of a single electron on a typical device can be quite significant. Such effects will eventually cause fundamental scaling and reliability problems. Random telegraph noise (RTN) phenomenon arising from electron emission and capture at an interface trap site [1.24]-[1.27] has been recognized as a new scaling concern in flash memory [1-28]-[1-33]. Typical two-level RTN pattern is shown in Fig.
1.2. Vt fluctuations originated from a large-amplitude RTN tail will cause a read error and become a prominent issue in designing a multilevel-cell (MLC) flash memory in 45nm technology node and beyond as shown in Fig. 1.3[1-30]. Fig. 1.4(a) shows that the worst case of RTN induced Vt shift is over 0.3V in 50 nanometer technology node [1-31]. Fig. 1.4(b) tells us that such large RTN tail may cause a read error in multilevel-cell flash memory application and requires the use of error code correction.
Another category of discrete charge storage flash memories are to use nano-crystals as storage nodes. Many different types of nano-crystals from semiconductors (Si, Ge) to metals (W, Au) have been proposed [1-34], [1-35]. Recently, a HfO2 dielectric dot flash memory with hot electron program/hot hole erase was presented with superior characteristics in terms of a large memory window, fast P/E speed, and long charge retention time [1-36]. As compared to semiconductor/metal dots, electrons in a dielectric dot are stored in trap states rather than conduction states. Because trapped electrons have a very sharp wave-function distribution in space, size quantization effect is not expected for the programmed electrons in a dielectric dot.
1.2 Description of the Problem
Negative bias temperature instability (NBTI) has been recognized as a major
reliability concern in ultra-thin dielectric pMOSFETs. Compared to SiO2 gate dielectric, the NBTI in high-k has been less explored. We employ the fast transient measurement technique to reduce the post-stress transient effect due to charge trapping/detrapping in high-k dielectric.
Two-bits/cell NOR-type SONOS flash memory has been realized by storing bit charges in two sides of a channel by channel hot electron (CHE) program and band-to-band tunneling (BTBT) hot hole erase. The control of program/erase charge lateral distributions of each bit is a major thrust to improve cell performance and scalability. Many attempts have been made in the past to characterize a trapped charge lateral profile in a SONOS cell. Two lateral profiling techniques were often used, a charge pumping (CP) method and an inverse I-V modeling approach. The CP current is too small to be measured. The inverse I-V modeling requires the knowledge of a two-dimensional device doping profile and does not yield a unique solution. The technique to characterize the charge profile, which is suitable for a small area cell and does not need a 2D numerical device simulation, is needed. Since RTN is very sensitive to a local potential change near the trap, it can be used as internal probe to detect a variation in a trapped charge density during program, erase and retention.
In recent years, RTN issues in FG flash device are intensively studied. Less works were done on RTN issues in charge trapping memory, i.e. SONOS. Especially, the difference dependence on program charge between FG and SONOS has never shown in the report until. The program charge effects on RTN amplitudes in floating gate flash and SONOS flash were investigated in detail.
1.3 Organization of the Dissertation
The scope of this thesis mainly focuses on reliability concerns of NBTI in high-k gate dielectric and RTN in nitride-based storage memory, which are schematically illustrated in Fig. 1.4. Following the introduction, the characterization of post-NBTI current instability in HfSiON gate dielectric pMOSFETs is demonstrated in Chapter 2.
Bipolar charge detrapping model is proposed and successfully applied to explain the experimental result. Described in Chapter 3 is a novel RTN-based technique for direct characterization of program/erase charge lateral distribution and retention mechanism in silicon nitride. In the chapter 4, we will investigate program charge effects on RTN amplitudes in floating gate flash and SONOS flash. The RTN measurement is performed in planar SONOS cells and floating-gate cells in erase state and program state, respectively. A SONOS cell has a wide spread in RTN amplitudes after programming while a floating gate cell has identical RTN amplitudes in erase and program states at the same read current level. Our result shows that the wide spread of program-state RTN amplitudes in a SONOS cell is attributed to a current-path percolation effect caused by random discrete nitride charges. In Chapter 5, the charge loss mechanism in a hafnium oxide (HfO2) dielectric dot flash memory is investigated. The temperature and time dependence of a charge loss induced gate leakage current in a large area cell are discussed. A thermally activated tunneling front model is proposed to account for the charge loss behavior in a HfO2 dot flash memory. Finally, conclusions are drawn in Chapter 6.