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HK IL

Si

E

F

(a)

(b)

poly-gate

HK IL

Si

E

F

poly-gate

HK IL

Si

E

F

(a)

(b)

Fig. 5.10 Illustration of the energy band diagram in relaxation phase. (a) Trapped electron emission to the gate, and (b) trapped hole emission to the substrate.

2.8 3.0 3.2

and (b) trapped holes. The extracted activation energy is 0.2eV for electrons and 0.14eV for holes.

Chapter 6 Conclusions

In short, this dissertation has involved the reliability issues in high-k gate dielectric pMOSFETs and charge trapping storage Flash memory. The subjects that have been comprehensively discussed including the post-NBTI behavior in high-k pMOSFETs, a novel RTS-based technique to characterize injected charge in SONOS flash cell, program charge effect on RTN amplitude in a flash cell, and retention mechanism in HfO2 dot flash memory. Contributions of each subject in this work are summarized as follows.

First, post-NBT stress current instability due to electron detrapping and hole detrapping in a high-k gate dielectric pMOSFET has been explored. Post-stress current recovery and degradation modes are observed. Our study shows that electron trapping is more likely to occur as NBT stress voltage and temperature increase. The presence of electron trapping complicates the modeling and characterization of NBTI. In order to extrapolate a reliable NBTI lifetime, electron trapping effects should be carefully considered in voltage/temperature accelerated stress.

Next, a novel RTS method is proposed to characterize program and erase charge lateral spread in a SONOS flash memory without the need to know a doping profile.

In the RTS method, the τce is very sensitive to program/erase/retention charges. It exhibits an exponential dependence on a local potential, as compared to a linear dependence in the CP method. The RTS method can provide a better resolution than

a charge pumping method or an inverse I-V modeling approach. A mismatch between program electrons and erase holes is shown by this method. Read current instability due to nitride charge vertical loss and random telegraph noise is directly observed.

Read failure due to a large amplitude RTN tail is an urgent issue in flash memory scaling. Random program charge effects in a planar SONOS cell on RTN have been characterized and simulated. In a FG cell, the RTN tail is mainly attributed to random substrate dopants while in a SONOS cell the percolation path and thus the amplitude of RTN are determined by both substrate dopants and program charges.

Our simulation shows that random program charges have a large effect on RTN. This effect has to be considered in RTN modeling in a program state of a MLC SONOS.

Finally, the charge loss mechanism in a HfO2 dot flash cell is investigated by characterizing a charge loss induced gate leakage current. The Frenkel-Poole emission model is not suitable for charge loss in the cell. A thermally activated tunneling front model is proposed. Our model can well explain the measured temperature and the retention time dependence of a gate leakage current.

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Chapter 3

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Chapter 4

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“High performance multi-bit nonvolatile HfO2 nanocrystal memory using spinodal phase separation of hafnium silicate,” in IEDM Tech.

Dig., pp. 1080-1082, 2004

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Electron Devices, vol. 54, pp. 90-97, 2007

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Solid-St. Electron., vol.36, pp. 1401-1416, 1993

Chapter 5

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[5.2] Campbell, J.P., Cheung, K.P., Suehle, and J.S. Oates, A., “The fast initial threshold voltage shift: NBTI or high-field stress,” IEEE Int. Reliability Phys. Symp., 2008, pp. 72-78

[5.3] Campbell, J.P., Cheung, K.P., Suehle, and J.S. Oates, A., “Electron trapping: An unexpected mechanism of NBTI and its implications,” in VLSI Symp. Tech. Dig., 2008, pp. 76-77

[5.4] C. J. Tang, H. C. Ma, T. Wang, C. T. Chan, and C. S. Chang, “Bipolar charge trapping induced anomalous negative bias-temperature instability in HfSiON gate dielectric pMOSFETs,” IEEE Trans. Device and Materials Reliability, vol. 7, no. 4, pp. 518-523, Dec. 2007

[5.5] T. Wang, C.T. Chan, C.J. Tang, C.W. Tsai, Wang, H.C.-H, M.H. Chi,

trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient,” IEEE Trans. Electron Devices, vol. 53, pp. 1073-1079, May, 2006

[5.6] C.T. Chan, C.J. Tang, T. Wang, H.C.H. Wang, and D.D. Tang, “Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET’s, “ in IEDM Tech. Dig., pp.571-574, 2005

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