Layout

Fig. 4.9 Improved “ balanced ring ” technique of this work for reduction of quadratic errors (a) rings (1 and 6) versus rings (3 and 4)

d d d d d d d d 190 122 182 d d d d d d d d

Fig. 4.9 Improved “ balanced ring ” technique of this work for reduction of quadratic errors (b) rings (2 and 5) versus rings (7)

d d d d d d d d 190 122 182 d d d d d d d d

Fig. 4.10 Selection sequence for MSB part of input code for improved “balanced-ring”

technique in Fig. 4.9

The layout of the DAC plays an important role since the random mismatch of current source due to process variation will degrade the accuracy of the DAC significantly. Thus we should pay mode attention to the floor plan of the DAC and special layout technique should be used, like [6] , [8] and [10] . To compensate for symmetrical and graded errors caused by temperature, process, and electrical gradients, special switching schemes should be

implemented.

In this design a floor plan of current cell matrix called improved “Balanced-ring” is used, as shown in Fig. 4.10. In the improved “balanced-ring” technique, the array is

subdivided into rings as shown by rings 1 to 7. First, we add up the quadratic errors of the cells within each ring. Then, starting from the ring 1 and 6, we determine how many of the ring 3 and 4 are required to cancel the error in ring 1 and ring 6. It turns out that four inner rings will do the job as shown in Fig. 4.9(a). Proceeding the same way for the remaining rings results in the selection of rings 2 and 5 for ring 7, is seen in Fig. 4.9(b). Now in each step we select the cells from counterpart rings (e.g., ring 1 and 6 versus rings 3 and 4) in a way that avoids accumulation of quadratic errors, as described above. Of course all these selections also obey the procedure.

Dummy cells and bias circuits can be placed in the “d” cell matrix. But additional rows or columns of dummy current source will not cause significant area increase of the current cell matrix.

The digital part of the DAC is placed on the left and the current cell matrix is placed on the right. To minimize the systematic error introduced by the voltage drop in the ground lines of the current-source transistors, wide sheets of metal have been used. Special care has been taken to realize a symmetrical interconnection array in order not to degree the matching performance. The power domains were separated into three parts: analog, digital and guard ring to avoid the analog section disturbed by the transient current of logic switching. The pins for ground and output were assigned more than one because of reducing the IR drop effect and parasitic inductance. In the current source array, dummy cells were adopted to lower the edge effect and can be treated as decoupling capacitor on the sensitive bias nodes. They are created by dummy transistor with body, source and drain all connected.

The chip will be fabricated with TSMC 0.18 µm mixed signal technology. The final layout was shown in the Fig. 4.11. These numbers in the graph means the pin orientation in the package. The active die size only has 1.615 µm².

Fig. 4.11 The Final Layout

4.5 Summary

A 12-bit 500-MSamples/s current–steering CMOS D/A converter is designed in this chapter. The architecture is shown first. Then, the design consideration and circuit diagram of each sub-block is described in each section. Finally, the layout concern and the switching scheme of current cell matrix have also been discussed. Since the DAC has been designed, the simulation and result of this DAC should also be presented to test the performance. This will be done in the next chapter.

Chapter 5

Simulation and Measurement Results

This current DAC has been designed and laid out by using the TSMC 0.18 µm CMOS Mixed-Signal process with one poly and six mentals. In this chapter, we present simulation resultant and the testing environment. The measured results are presented in this chapter, too.

5.1 Simulation results

The major target specification for SFDR of this paper, a 12-bit 500-MSample/s D/A converter, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to derive maximum benefit from this relatively advanced technology.

The sample rate is set to 500MHz at input frequency 1.46 MHz, 10.25 MHz, 38.57 MHz, 49.32 MHz, 72.75 MHz, 96.19 MHz, 110.84 MHz and 171.39 MHz, respectively. A simulate sine wave spectrum for Fs = 500 MHz and Fsig = 110.84 MHz is shown in Fig. 5.1. A simulate sine wave spectrum for F_s = 500 MHz and F_sig = 171.39 MHz is shown in Fig. 5.2.

Fig. 5.3 shows the SFDR of input frequency between 1.46 MHz and 171.39 MHz at the sample rate 500 MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) are shown in the Fig 5.4. The total simulation result of this DAC is summarized in Table 5-1.

Fig. 5.1 Sine wave spectrum for Fs = 500 MHz and Fsig = 110.84 MHz

Fig. 5.2 Sine wave spectrum for F_s = 500 MHz and F_sig = 171.39 MHz

Fig 5.3 The SFDR of input frequency between 1.46 MHz and 171.39 MHz at the sample rate 500 MHz

Fig 5.4 The differential nonlinearity (DNL) and integral nonlinearity (INL)

Table 5-1 The total simulation results of this DAC input digital code is generated by Agilent 16902B Logic analysis System. The differential output of the DAC is converted to a signal-ended output by using an active probe to provide rejection of common mode noise and even order distortion. This signal-ended output is measured by Agilent E4440A 3 Hz-26 GHz PSA Series Spectrum Analyzer to get spectrum performance. The Voltage transient output signals are measured by Agilent 34401 Digital Multimeter. Two precise power supplies are used to generate both analog and digital supply.

Fig. 5.5 Testing Setup

The analog and digital power supplies are generated by the application of the LM317 adjustable regulators shown in Fig. 5.6. The capacitor C1 is used to improve the ripple rejection and capacitor C2 is the input bypass capacitor. The resistor R1 is the fixed resistor and resistor R2 is the precise variable resistor. The output voltage of the Fig. 5.6 can be expressed as

2

2 1

1.25 (1 )

out ADJ

V V R I R

= ⋅ + R ⋅ ⋅ (5.1)

Where I_ADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator.

By the way, the resistor R1 can use the low temperature coefficient of the metal film resistor to get the stable output voltage.

0.1 Fµ

1 Fµ

Fig. 5.6 Power Supply Regulator

5.2 Measurement Results

The sample rate is set to 100 MHz at input frequency 3 MHz, 5.17 MHz, 12.83 MHz, 20.67 MHz and 34.33 MHz, respectively. A measured sine wave spectrum for F_s = 100 MHz and Fsig = 3 MHz is shown in Fig. 5.7. A measured sine wave spectrum for Fs = 100 MHz and F_sig = 5.17 MHz is shown in Fig. 5.8. Fig. 5.9 shows the SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate 100 MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) are shown in the Fig 5.10. The total measured result of this DAC is summarized in Table 5-2 and the die microphotograph is shown in Fig. 5.11.

Fig. 5.7 Sine wave spectrum for Fs = 100 MHz and Fsig = 3 MHz

Fig. 5.8 Sine wave spectrum for F_s = 100 MHz and F_sig = 5.17 MHz

Fig 5.9 The SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate 100 MHz

Fig 5.10 The differential nonlinearity (DNL) and integral nonlinearity (INL)

Fig 5.11 The die microphotograph

Table 5-2 The total measurement results of this DAC

Process

TSMC 0.18 µm CMOS Mixed-Signal

Supply Voltage

Digital supply 1.8V Analog supply 3.3V

Sampling Frequency 100 MHz

DNL < 3.3 LSB

INL < 5.4 LSB

SFDR(Fin = 3 MHz) 47 dB @ CLK = 100 MHz

Power Dissipation 128 mW

Active Area 1.615 mm²

61

Chapter 6

Conclusions and Future Work

In this thesis, the implementation of 12-bit DAC is presented to operate at high update rate.

To design a high speed DAC, the current steering architecture is a suitable candidate. But the nonidealities effects of the DAC will affect the overall system performance. The current source is properly designed to reduce the nonlinearity caused by finite output impedance of current source.

To overcome the random error and systematic error, the proper area of current source is selected and special layout technique is used. It can improve quadratic error and cancel gradient error. A high speed, low crossing point latch is implemented to compensate the error at the DAC output due to switching in the current cells. The DAC is fabricated by 0.18 µm 1P6M CMOS

Mixed-Signal. The active area of the DAC is about 1.615 mm² and the total area is about 2.896 mm². Besides, the power dissipation is 128 mW. The measure result shows that with the signal frequency of 34.33 MHz at the update rate of 100MHz, the SFDR is 32 dB. The differential nonlinearity and integral nonlinearity are below 3.3 and 5.4 least significant bits (LSB’s).

The DAC can be improved from several points of view in the future. First, Several recommendations were proposed for digital signal integrity. Adding buffer is the best way to overcome the heavy load. The drive ability of digital logics should be enhanced to defend the largest parasitic capacitance. We may choose redesign of the latch cell and thermometer coded to achieve the above discussion. Second, due to lack of considering the parasitic loading effect caused by the layout, the post-layout dynamic performance simulation results will be degraded than the pre-layout simulation at high input frequency. Therefore, the DAC should be designed to keep enough margins to endure the loading effect and the floor plan should be modified to

decrease the parasitic loading. Finally, the clock should be designed carefully because the current DAC operated at high speed. And pay more attention to routing between circuit blocks. The DAC can be taped out several times and compared the performance by using differential layout

methods.

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