Chapter 3. Nonidealities in Current-Steering DAC
3.4 Clock Jitter
Jitter in the clock that strobes the synchronization of the switching driver used for
driving the current cell can significantly degrade the performance of the current steering DAC.
The digital data to the switch signal is aligned globally with a latch to reduce the time skew.
Therefore, a good clock distribution is needed. Fig. 3.9 shows a tree structure with
clock-distribution approaches, which is suitable for high speed and high accuracy. The clock trees improve the skew to a single- line clock distribution.
Since the jitter assed to a clock signal inside the chip increases linearity with the buffer stages used to generate the clock, it is important to minimize the number of buffers used to generate the clock signal that drives the sensitive synchronization flip-flops. Besides, an on-chip PLL can be designed for a DAC since a clock source with low jitter needed for the DAC can be exported more easily by PLL circuits than an external clock source.
Figure 3.9 Clock Tree Structure
3.5 Summary
The nonidealities of current steering DAC is discussed in this chapter, including finite output impedance of current source, current source mismatch, nonidealities due to switching in current cells, and clock jitter. In order to design a high-speed and high-resolution current steering DAC, we should pay more attention to these nonidealities. The approaches to improve the nonidealities are also mentioned in this chapter.
Chapter 4
DAC Circuit Design
In this chapter, the designed architecture of a 12-bit 500-MSamples/s current–steering CMOS D/A converter is introduced at first. Then each block of the DAC is presented and the circuit design is discussed. To design a high speed and high resolution DAC, we should pay more attentions to choose the proper architecture that can achieve a balance between good static and dynamic specifications versus a reasonable circuit power, area, and complexity.
Besides, special layout technique is also presented to compensate the systematic and gradient errors, as mentioned in chapter 3.
4.1 The Architecture of DAC
Base on the discussions of different architectures of DACs, we choose the segmented architecture because this architecture can get a compromise between static and dynamic performance. Fig. 4.1 shows the overview of the specifications of thermometer coded, binary weighted, and segmented implementations of current steering DAC. The binary weighted architecture has advantages of small area, low power consumption and less complexity.
However, this architecture has large DNL error, glitch energy and not guaranteed monotonicity, which will degrade the performance of the DAC. The thermometer coded architecture has a contrary advantages and disadvantages to the binary weighted architecture.
To keep the advantages of both binary weighted and thermometer coded architectures, segmented architecture is a good candidate and is used in this thesis.
Figure 4.1 Overview of Binary Weighted, Thermometer Coded, and Segmented Implementations
The architecture of a 12-bit 500-MSamples/s current–steering CMOS D/A converter presented in this thesis is shown in Fig. 4.2. There are several blocks in this DAC, including digital circuits, latches, current cells, and bias circuit. The input binary codes are either processed through digital circuits, then changed to thermometer codes (A11 – A4) or simply equally delayed (A3 – A0). The processed signals then pass through the latches to keep synchronization used for driving switches of the current cells. In addition to synchronization, the latches can also reduce the glitch effect due to the drain voltage fluctuations of current sources. Finally, the current cell matrix can provide differential output currents controlled by
the switches whose input signals have been synchronized. In the following, all the sub-circuitry of this DAC will be further discussed.
Fig. 4.2 Block Diagram and Floorplan of the Segmented 12-bit DAC
4.2 Digital Circuits
In a segmented current-steering DAC, the function of the digital circuits it to convert the binary code to either thermometer code or only delayed the binary code. To design the digital circuits, several issues should be taken into account:
¾ High speed operation
¾ Circuit complexity
¾ Power consumption
From the issues, several compromises between decoder architecture, coding scheme and circuit implementation of digital circuits should be considered carefully.
In order to use the segmented architecture, we should determine the number of bits for MSB’s and LSB’s that are thermometer decoded and delay equalized, individually. To achieve a good DNL specification and glitch energy, the number of bits implemented in the binary weighted part of the DAC has to be small. However the number of output lines of the thermometer encoder increases with 2N where N is the number of bits, resulting in complex logic and large input capacitance. A direct consequence is often a reduction in the maximum operating speed. Equally important is the fact that the area used by the decoding and
interconnections inside the matrix increases, and consequently the process and electric systematic errors become more difficult to compensate [6]. So the DAC has a 8 + 4 segmented architecture: first, the eight most significant bits (MSB’s) are linearly decoded;
second, the four least significant bits (LSB’s) are binary weighted.
4.2.1 Thermometer decoder
Fig. 4.3 The 4-bit thermometer decoder logic
From the Fig. 4.2, the system block diagram reveals that one kind of 8-bit thermometer decoder is essential. The 8-bit thermometer decoder is divided into tow 4-bit thermometer
decoder. Row-column selection decoding is a simple method to supply high speed
transformation [6]. In high speed realization, the adopted decoder can limit the clock rate of the D/A converter. Fig. 4.3 shows the row-column selection decoding methodology. Two 4-bit thermometer decoder forms the major part of the 8-bit thermometer decoder in Fig. 4.4.
Fig. 4.4 The Digital Circuit used in the DAC
4.2.2 High speed latch
The dynamic performance degradation of a current-steering DAC can be caused by several reasons associated with current source switching. Some important issues that have been identified to cause dynamic limitations are :
¾ Imperfect synchronization of the control signals at the switches.
¾ Drain-voltage variations of the current-source transistors caused by the fact that both switch transistors are simultaneously in the off state.
¾ Coupling of the control signals through the Cgd of the switches to the output.
To minimize the three effects, a well-designed synchronized driver is used. The high speed, low glitch latch is illustrated in Fig. 4.5(a). It provides two complementary signals needed at the input of the current switches.
In the conventional latch, both switches will be off for a short period. As a result, the capacitance at the drain of the current source transistor will be charged and then the current source will turn off. To recover the normal operation, the current source must progress through the linear region and back into saturation. Hence, turning off the current source not only slows down the speed but also increases glitch at the output. To solve the problem, the function of this latch is designed to shift down the crossing point of the differential signals used for driving the switches of the current cell.
The latch used here is a rise/fall time based driver. In order to obtain instantaneous change for output node with falling input, extra PMOS transistors (M1 and M2) are placed in parallel with each other cross-coupled at the top of the circuit. When the transitions of input signals (high Æ low or low Æ high) occur, the transistors M3-M10 will immediately change their states. However, the crossed-coupled PMOS transistors M1 and M2 will hold their states for a short period. After these transistors change their states, the charging speed will be increased. Thus, the combination of the (µn / µp) scaled PMOS transistors and the PMOS positive feedback loop results in the rise time that is much faster than the fall time of the driver circuit. Due to the use of two additional inverters at the output of the driver and properly sizing the transistors of the whole latch, a lower crossing point can be realized. Fig. 2 (b) shows the voltage waveforms of the differential outputs, Q and Q . This latch not only performs the final synchronization of the signals used for switching different current cells but
also reduces the delay between the different digital decoders.
D D
CLK
CLK CLK
CLK
Q Q
(a)
Q
Q
(b)
Fig. 4.5 (a) Dynamic Latch Schematic Diagram (b) Output Signals
4.3 Analog Circuits
To generate the accurate current, several concerns should be taken into account. First, the size of the current sources should be properly designed to reduce the mismatch error between different current sources due to the fabrication. Second, the finite output impedance of each current source is designed large enough to get a good static performance. Finally, a bias circuit used to generate the bias current of current source is also required. The design
considerations and circuit implementation of each circuit is described in next subsections.
4.3.1 Implementation of Switch Unit Current Cell
The PMOS current source has two advantages. PMOS devices built in n-well are thus shielded from the substrate. PMOS has less flicker noise than NMOS. The circuit schematic of the cascode switch current cell is shown in Fig. 4.6. The output impedance of the current source which is ro1+ro2⋅ +
(
1 gm1⋅ro1)
is very large.In the following content, we will continue to find out what size of current source transistor should be used. Design flow of the current cell’s size is shown in Fig. 4.7. If we want to decide the size of the current cell, we need INL_yield , process parameter (Aβ and AVT), and gate overdrive voltage (VGS-VT) . We also need to consider DAC specification, including INL and SFDR.
OUT OUT
0 BIAS
1 BIAS
IN IN
Fig. 4.6 The circuit schematic of cascode switch current cell
( )I I
Fig. 4.7 Design flow of the current cell’s size
There was discussion of spatial errors in current source array in the former section.
Actually it is convenient to distinguish these errors by two parts: one is systematical error and the other is random error. These errors can disturb the static accuracy and dynamic
performance of D/A converter. Generally speaking, systematical error can be subdivided into four kinds:
¾ Process gradients
¾ Voltage drops in the supply line
¾ Thermal gradients
¾ Output impedance of the current source
The switching scheme was to average the spatial errors in the current source array caused by process gradients. It also suppressed the nonlinearity contributed by thermal gradients. The residues are left for the following sections. So turn back our attention on our topic of this section: How random errors degrade the accuracy of our designs? According to
[14], the identical device with the same size and similar geometry was suffered random mismatch due to the fabrication in real world.
For a current-steering DAC, the INL is mainly determined by the matching behavior of the current sources. A parameter that is well suited for expressing this technology versus DAC specification relation is the INL_yield. This yield figure is defined as the percentage of functional D/A converters with an INL specification smaller than half an LSB (least
significant bit).
Finite output impedance is also an error source that will cause performance degradation of the current-steering DAC. Base on the analysis in section 3.1, we can design the proper current source output impedance to get both good static and dynamic performance. From Fig.
4.7, we can find that in order to meet the specification .Also, the size of the switches should be as small as possible to avoid the effects of both clock feedthrough and charge injection during the transition of the signal at switches.
4.3.2 Reference Current Generation
Fig. 4.8 shows the biasing scheme for the cascode current sources. An external resistor, R , is used to generate the reference current. The NMOS sections of the biasing circuits are labeled as “global biasing” while the PMOS sections are labeled as “local biasing.” The cascode current mirror in the current cell can be used to reduce short-channel effects and increase the output impedance, but it will limit the signal swing. In order to reduce this limitation, a wide-swing cascode current mirror bias scheme is shown in “local biasing” of Fig. 4.8.
Fig 4.8 The Circuit Schematic of the Bias Circuit
4.4 Layout
Fig. 4.9 Improved “ balanced ring ” technique of this work for reduction of quadratic errors (a) rings (1 and 6) versus rings (3 and 4)
d d d d d d d d 190 122 182 d d d d d d d d
Fig. 4.9 Improved “ balanced ring ” technique of this work for reduction of quadratic errors (b) rings (2 and 5) versus rings (7)
d d d d d d d d 190 122 182 d d d d d d d d
Fig. 4.10 Selection sequence for MSB part of input code for improved “balanced-ring”
technique in Fig. 4.9
The layout of the DAC plays an important role since the random mismatch of current source due to process variation will degrade the accuracy of the DAC significantly. Thus we should pay mode attention to the floor plan of the DAC and special layout technique should be used, like [6] , [8] and [10] . To compensate for symmetrical and graded errors caused by temperature, process, and electrical gradients, special switching schemes should be
implemented.
In this design a floor plan of current cell matrix called improved “Balanced-ring” is used, as shown in Fig. 4.10. In the improved “balanced-ring” technique, the array is
subdivided into rings as shown by rings 1 to 7. First, we add up the quadratic errors of the cells within each ring. Then, starting from the ring 1 and 6, we determine how many of the ring 3 and 4 are required to cancel the error in ring 1 and ring 6. It turns out that four inner rings will do the job as shown in Fig. 4.9(a). Proceeding the same way for the remaining rings results in the selection of rings 2 and 5 for ring 7, is seen in Fig. 4.9(b). Now in each step we select the cells from counterpart rings (e.g., ring 1 and 6 versus rings 3 and 4) in a way that avoids accumulation of quadratic errors, as described above. Of course all these selections also obey the procedure.
Dummy cells and bias circuits can be placed in the “d” cell matrix. But additional rows or columns of dummy current source will not cause significant area increase of the current cell matrix.
The digital part of the DAC is placed on the left and the current cell matrix is placed on the right. To minimize the systematic error introduced by the voltage drop in the ground lines of the current-source transistors, wide sheets of metal have been used. Special care has been taken to realize a symmetrical interconnection array in order not to degree the matching performance. The power domains were separated into three parts: analog, digital and guard ring to avoid the analog section disturbed by the transient current of logic switching. The pins for ground and output were assigned more than one because of reducing the IR drop effect and parasitic inductance. In the current source array, dummy cells were adopted to lower the edge effect and can be treated as decoupling capacitor on the sensitive bias nodes. They are created by dummy transistor with body, source and drain all connected.
The chip will be fabricated with TSMC 0.18 µm mixed signal technology. The final layout was shown in the Fig. 4.11. These numbers in the graph means the pin orientation in the package. The active die size only has 1.615 µm2.
Fig. 4.11 The Final Layout
4.5 Summary
A 12-bit 500-MSamples/s current–steering CMOS D/A converter is designed in this chapter. The architecture is shown first. Then, the design consideration and circuit diagram of each sub-block is described in each section. Finally, the layout concern and the switching scheme of current cell matrix have also been discussed. Since the DAC has been designed, the simulation and result of this DAC should also be presented to test the performance. This will be done in the next chapter.
Chapter 5
Simulation and Measurement Results
This current DAC has been designed and laid out by using the TSMC 0.18 µm CMOS Mixed-Signal process with one poly and six mentals. In this chapter, we present simulation resultant and the testing environment. The measured results are presented in this chapter, too.
5.1 Simulation results
The major target specification for SFDR of this paper, a 12-bit 500-MSample/s D/A converter, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to derive maximum benefit from this relatively advanced technology.
The sample rate is set to 500MHz at input frequency 1.46 MHz, 10.25 MHz, 38.57 MHz, 49.32 MHz, 72.75 MHz, 96.19 MHz, 110.84 MHz and 171.39 MHz, respectively. A simulate sine wave spectrum for Fs = 500 MHz and Fsig = 110.84 MHz is shown in Fig. 5.1. A simulate sine wave spectrum for Fs = 500 MHz and Fsig = 171.39 MHz is shown in Fig. 5.2.
Fig. 5.3 shows the SFDR of input frequency between 1.46 MHz and 171.39 MHz at the sample rate 500 MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) are shown in the Fig 5.4. The total simulation result of this DAC is summarized in Table 5-1.
Fig. 5.1 Sine wave spectrum for Fs = 500 MHz and Fsig = 110.84 MHz
Fig. 5.2 Sine wave spectrum for Fs = 500 MHz and Fsig = 171.39 MHz
Fig 5.3 The SFDR of input frequency between 1.46 MHz and 171.39 MHz at the sample rate 500 MHz
Fig 5.4 The differential nonlinearity (DNL) and integral nonlinearity (INL)
Table 5-1 The total simulation results of this DAC input digital code is generated by Agilent 16902B Logic analysis System. The differential output of the DAC is converted to a signal-ended output by using an active probe to provide rejection of common mode noise and even order distortion. This signal-ended output is measured by Agilent E4440A 3 Hz-26 GHz PSA Series Spectrum Analyzer to get spectrum performance. The Voltage transient output signals are measured by Agilent 34401 Digital Multimeter. Two precise power supplies are used to generate both analog and digital supply.
Fig. 5.5 Testing Setup
The analog and digital power supplies are generated by the application of the LM317 adjustable regulators shown in Fig. 5.6. The capacitor C1 is used to improve the ripple rejection and capacitor C2 is the input bypass capacitor. The resistor R1 is the fixed resistor and resistor R2 is the precise variable resistor. The output voltage of the Fig. 5.6 can be expressed as
2
2 1
1.25 (1 )
out ADJ
V V R I R
= ⋅ + R ⋅ ⋅ (5.1)
Where IADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator.
By the way, the resistor R1 can use the low temperature coefficient of the metal film resistor to get the stable output voltage.
0.1 Fµ
1 Fµ
Fig. 5.6 Power Supply Regulator
5.2 Measurement Results
The sample rate is set to 100 MHz at input frequency 3 MHz, 5.17 MHz, 12.83 MHz, 20.67 MHz and 34.33 MHz, respectively. A measured sine wave spectrum for Fs = 100 MHz and Fsig = 3 MHz is shown in Fig. 5.7. A measured sine wave spectrum for Fs = 100 MHz and Fsig = 5.17 MHz is shown in Fig. 5.8. Fig. 5.9 shows the SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate 100 MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) are shown in the Fig 5.10. The total measured result of this DAC is summarized in Table 5-2 and the die microphotograph is shown in Fig. 5.11.
Fig. 5.7 Sine wave spectrum for Fs = 100 MHz and Fsig = 3 MHz
Fig. 5.8 Sine wave spectrum for Fs = 100 MHz and Fsig = 5.17 MHz
Fig 5.9 The SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate 100 MHz
Fig 5.10 The differential nonlinearity (DNL) and integral nonlinearity (INL)
Fig 5.11 The die microphotograph
Table 5-2 The total measurement results of this DAC
Process
TSMC 0.18 µm CMOS Mixed-Signal
Supply Voltage
Digital supply 1.8V Analog supply 3.3V
Sampling Frequency 100 MHz
DNL < 3.3 LSB
INL < 5.4 LSB
SFDR(Fin = 3 MHz) 47 dB @ CLK = 100 MHz
Power Dissipation 128 mW
Active Area 1.615 mm2
61
Chapter 6
Conclusions and Future Work
In this thesis, the implementation of 12-bit DAC is presented to operate at high update rate.
In this thesis, the implementation of 12-bit DAC is presented to operate at high update rate.