Chapter 1. Introduction
1.2 Organization
This thesis is organized as six chapters. Brief content of each chapter is described as follows. In chapter2, the fundamental concepts and architectures of DAC are described first.
In addition, the static and dynamic specifications that will impact a DAC’s performance are discussed. Chapter 3 presents the nonidealities of current-steering DAC, including finite output impedance, mismatch in current source, timing nonidealities, and nonidealities due to switching in a current-steering DAC. In Chapter 4, based on the consideration discussed in chapter 2 and chapter 3, the design and implementation of a 12-bit 500MHz current-steering segmented architecture DAC is described in chapter 4.
Chapter 5 presents the simulation and measurement results. Conclusion and future work are in chapter 6.
Chapter 2
Digital-to-Analog Converter Architecture
Digital-to-analog conversion is an essential function in data processing systems. D/A converters (DACs) interface the digital output of signal processors with the analog word. The digital-to-analog (D/A) converts a discrete amplitude, discrete time signal to a continuous amplitude, continuous time output.
If the DAC generate large glitches during switching from one code to another, then a
deglitching circuit is used to mask the glitches. Finally a low-pass filter is required to suppress the sharp edges introduced by the DAC [22].
In this chapter, the fundamental of DAC and different techniques for converting a digital signal into an analog signal representation is presented. The approaches differ in speed, chip area, power efficiency, achievable accuracy, etc.
2.1 Ideal D/A converter
A digital-to-analog converter produces an analog output Vout that is proportional to the digital input Bin. For a N-bit D/A converter shown in Fig. 2.1, the output Vout can be
significant bit (MSB).
Fig. 2.1 Block Diagram of a N-bit D/A converter
2.2 Static Performance of DACs
Due to non-ideal circuit elements in the actual implementation of a data converter the code transition points in the transfer function will be moved as illustrated in Fig. 2.2.
, 1 ∆ Xa k+
,
Xa k
,
Xa m ,
Xa m
Fig. 2.2 Non-ideal transfer function with INL and DNL errors of DAC
To distinguish between the actual and ideal values in the data converters, all actual values are indicated with a ~. This means that Xa,k corresponds to the ideal analog value for digital code Xd,k while Xa k, corresponds to the actual value.
The step size in the non-ideal data converter deviates from the ideal size △ and this error is called the differential nonlinearity (DNL) error. For a DAC the DNL can be defined as the difference between two adjacent analog outputs minus the ideal step size, i.e.
DNLk =Xa k, +1−Xa k, − ∆ (2.4)
The DNL is often normalized with respect to the step size to get the relative error, i.e.
k Xa k, 1 Xa k,
DNL + − − ∆
= ∆
(2.5)
The above definitions are often most practical for DACs since the analog values can be directly measured at the output.
The total deviation of an analog value from the ideal value is called integral nonlinearity (INL). The normalized INL can be expressed as
The relation between INL and DNL is given by
The nonlinearity errors are usually measured using a low frequency input signal to exclude dynamic errors appearing at high signal frequencies. The DNL and INL are therefore usually used to characterize the static performance.
,
Xa k
, 1
Xa k+
Figure 2.3 A non-monotonic DAC
If the analog amplitude level of the converter increases with increasing digital code, the converter is monotonic. An example of a non-monotonic DAC is shown in Fig 2.3.
Monotonicity is guaranteed if the deviation from the best-fit straight line is less than half a LSB, i.e.
1
k 2
INL ≤ LSB for all k (2.8)
This implies that the DNL errors are less than one LSB , i.e.
k 1
DNL ≤ LSB for all k (2.9)
It should be noted that the above relations are sufficient to guarantee monotonicity, but it is possible to have a monotonic converter that does not meet the relations in (2.8) and (2.9).
There are some data converter architectures that are monotonic by design, e.g. a thermometer coded DAC.
2.3 Dynamic Performance of DACs
In addition to the static errors that are caused by mismatch in the components in the data converter, several other error sources will appear when the input signal change rapidly. These dynamic errors are often dependent on signal frequency and increases with signal amplitude and frequency. They appear in data converter but are usually more critical in DACs since the shape of the analog wave form determines the performance [2].
A number of dynamic effects arise when the output signal is changed between two samples. These dynamic error sources will have a large impact on the DAC performance, especially at high clock and signal frequencies. When the input of the DAC is changed, the analog output should ideally change from the ideal start value, Xa k, to the ideal final value,
,
Xa m see Fig. 2.4. Due to circuit imperfections the actual start and final values are Xa k, and
,
Xa m respectively. The output signal of an actual DAC can not change its value instantly. The time it takes for the output to settle within a certain accuracy of the final value, for instance 0.1%, is called the settling time Ts, and determines the highest possible speed of the circuit.
The settling can be divided in two phases, a non-linear slewing phase and a linear settling phase. The slewing phase should be as small as possible since it both increases the settling time and introduces distortion in the analog waveform. The slewing is normally
caused by a too small bias current in the circuit driving the output and is therefore increased for large steps when more current is needed.
,
Fig. 2.4 Actual output signal and ideal output signal (dashed) of a DAC
Glitches occur when the switching time of different bits in a DAC is unmatched. For a short period of time a false code could appear at the output. For example if the code transition is
0111……111 →
and the MSB switches faster than the LSBs, the code 1111……111 may be present for a short time This code represents the maximum value and hence a large glitch appears at the output.
The glitch adds a signal dependent error to the output signal that degrades the performance.
The effect on the output signal is determined by the energy of the glitch.
The clock feedthrough (CFT) can introduce both harmonic distortion and distortion
tones at multiples of the clock signal. It is caused by the finite overlap capacitance between the gate and drain terminals. In Fig. 2.5, when the gate control voltage CLK changes to high voltage, the PMOS turns off and Cov conducts the transition and changes the voltage stored on CL by an amount equal to
ov CLK
ov L
V C V
C C
∆ = + (2.10)
The CFT is reduced when reducing the capacitive coupling and therefore the switch transistor sizes should be small to decrease the size of the parasitic capacitances. However, with a smaller transistor, the on-resistance increases which may degrade the performance due to an increased settling time.
Figure 2.5 Clock Feedthrough for MOS switch
2.4 Charge Redistribution DAC
The charge redistribution DAC is a switch capacitor (SC) circuit, where the charge stored on a number of binary weighted capacitors is used to perform the conversion. Fig. 2.6
is an example of a N-bit converter. Typically, the weighted capacitors are created using a number of unit capacitors.
At time nT ( on phase ψ1 ), the bit bi determine which of the binary weighted capacitors that should be charged from the reference voltage,V ref . During this phase, the plates of capacitor CN are connected to ground and virtual ground at the input of the op amp, i.e., there is no charge on CN, and qN (nT) = 0. Capacitor CC is used for offset compensation.
The total charge on the binary weighted capacitors at time nT is given by
1 1
At time nT +Τ/2 , on phaseψ2 , the weighted capacitors are discharged since their plates are connected to DC and virtual grounds. The charge is redistributed to ground and CN . The charge onCN at the end of the settling is
The architecture in Fig. 2.6 is insensitive to offset voltage and finite gain of the amplifier. The limitations of the converter are the matching of the capacitors, the switch-on resistance, and finite bandwidth of the amplifier.
φ1
Fig. 2.6 The architecture of a N-bit charge-redistribution DAC
2.5 R-2R Ladder DAC
It is easy to construct a resistor-based binary-weighted DAC. But the resistance spread is very large for a large number of bits N. To reduce the large resistor ratios in a binary- weighted DAC, the R-2R ladder architecture is a good choice. An N-bit R-2R ladder architecture is shown in Fig. 2.7. The current sources are all equally large, and the switches are controlled by the bits bi. At every node, the impedance is always R. The output current is given by
This DAC architecture is power inefficient, since there is a current loss through the resistive network. Due to the fact that all current sources are equally large, the matching can
be improved. In a poor process, the resistors can be non-linear and contain signal-dependent capacitive parts yielding distortion. Time-skew between switching instants generates glitches in this architecture. In this R-2R ladder architecture there is the same amount of current through all switches, which makes the design of the switches simpler. However, the internal voltage nodes are still AC varying and therefore the current sources will have varying terminal voltages.
As a conclusion, one of the major advantages is that we only have a few number of different component sizes to implement, i.e., two resistor sizes, R and 2R, one current source size, and one type of current switch. This allows a more regular layout and since the current sources all have the same size. R-2R ladder DACs are more widely used in bipolar processes where high-quality resistors are available.
Fig. 2.7 An N-bit R-2R ladder DAC
2.6 Binary Weighted Current-Steering DAC
The switched-current (SI) technique is a common choice in a CMOS process, since the reference and sum elements as well as switches are relatively easy to be implemented. The general architecture of a binary weighted current-steering DAC is shown in Fig. 2.8.
The switches are controlled by the input bits, bi , where i = 0, 1, … , N-1 and N is the
number of bits. b0 is the LSB and the corresponding current source has the DC value ILSB . The source controlled by bit bi , i.e., the i -th LSB current source, is formed by connecting 2i LSB current sources (unit current sources) in parallel, hence the MSB current source has the DC value IMSB=2N-1ILSB. The use of unit element sources increases the matching of the sources. The output current,Iout , of the DAC shown in Fig.2.8 is given by
1
0 1 1
( ) 2 2N
out LSB LSB LSB N LSB
I k =I ⋅ +b I ⋅ + +b " − I ⋅b − =I ⋅k (2.16)
Where k is the digital input given by
1
The current-steering DAC has the advantage of being quite small for resolution below 10 bits and it is very fast. The major disadvantage is the sensitivity to device mismatch, glitches, and current source output impedance for higher number of bits. Another good property of the current-steering DAC is that its high power-efficiency since all power is directed to the output. The current-steering DAC is suitable for high-speed high-resolution applications, especially when special care is taken to improve the matching of the converter.
To achieve monotonicity, reduce the influence of glitches and reduce the sensitivity to matching errors, the DAC should be segmented into a coarse and fine part. The coarse part is realized by thermometer coded and fine part is kept binary weighted. This is referred to as a segmented converter and is discussed further.
LSB
Figure 2.8 An N-bit current-steering binary weighted DAC
2.7 Thermometer Coded DAC Architecture
The thermometer coded DAC differs from a binary one is that a thermometer-code has 2N-1 digital inputs to represent 2N different values. Each digital inputs control the current sources with equally large value, I. Fig.2.9 shows a N-bits example of thermometer coded current steering DAC converter. The binary input coded is encoded into a thermometer coded as illustrated in Table 2-1 for a 3-bit input example.
Monotonicity is guaranteed here since, when the binary input changes to the next higher value, one more digital value in the thermometer code goes high, causing additional current to be drawn out and forces the resistor output to go some amount high. The DNL and INL are improved compared to the binary version. The requirements on element matching are also relaxed. In fact, if the matching is within a 50% margin, the converter is still monotonic.
More importantly, a D/A converter based on a thermometer code greatly minimizes glitches, as compared to binary version, since banks of current sources are never exchanged at slightly different times when the output should be change by on 1LSB. The major drawback of thermometer-coded DAC is area, since for every LSB this architecture needs a current source, a switch, and a decoding circuit, as well as the binary to thermometer decoder.
1
Figure 2.9 A thermometer coded current-steering DAC with encoding circuit
Binary Thermometer Code
Table 2-1 Thermometer Code Representations for 3-Bit Binary Values
2.8 Hybrid DAC Architecture
As mentioned in the previous section, architectures based on different DACs suffer form several important drawbacks. First, they require tight device matching to achieve
monotonicity (DNL<1LSB). Second, they require exhibit large glitch impulse. Third, the decoding circuits may be complexity, and consume large area. Hybrid architecture is
commonly used to alleviate these problems. The M-bit Hybrid architecture is illustrated in Fig.
2.10 where each N-bit DAC can be of completely different types.
1
2
L
Fig. 2.10 Hybrid DACs use a combination of a number of different types of DACs
For instance, a popular hybrid converter architecture is the so called segmented architecture as show in Fig.2.11. This architecture is divided into a coarse sub-DAC and a binary-weighted fine sub-DAC. In other words, for a resolution of K = M+N, the M most significant bits are converted to thermometer code and drive a 2M-1 unit segmented array, while the remaining N bits are directly applied to an N-bit binary array.
The choice of M and N in general depends on the matching of the current source, the tolerable glitch, and area. When increasing M, the size of the encoder grows exponentially and a larger amount of switches and interconnection are needed. However, the advantages are the improved device matching and linearity over binary weighted DACs. One of the key issues is to find the optimum number of MSBs to encode into a thermometer code. Reasonable size for M is in the range from 4-8.
Fig. 2.11 An N-bit segmented DAC where M MSBs are thermometer coded
2.9 Summary
In this chapter, the fundamental of the digital-to-analog Converters (DACs) is presented first. The performance parameters used to characterize the specifications of DAC is also described. Also, different types of Nyquist-Rate DACs are introduced.
According to the discussions of the advantages and disadvantages for different type DACs, we can choose the suitable architecture for our applications among several trade-offs, like power consumption, speed, and die area.
Chapter 3
Nonidealities in Current-Steering DAC
Current-steering DAC is a popular topology when high speed and high resolution is needed since it can drive resistive loads directly, and do not require high speed amplifiers at the output. A differential output type current steering DAC is preferred because it can lower the common mode noise and second harmonic distortion. But it still has some nonidealities that will degrade the performance of the DAC. The errors sources that cause the nonidealities include finite output impedance effect, current source mismatch, timing nonidealities and nonidealities due to switching the current cells.
The effects of nonidealities mentioned above on the performance of a current-steering DAC can be categorized into two groups:
Increased Random Noise : An increase in the noise floor in the signal band reduces the
dynamic range of the converter. Sources of random noise include the thermal noise of
transistors and resistors and the coupling of noise from digital circuitry into the analog circuits through the common substrate, package, and supply lines.
Harmonic Distortion : Signal-dependent nonidealities result in harmonic distortion in the
DAC output. Ideally, even harmonics are completely cancelled through the use of a differential topology, but mismatch between the differential paths results in some residual even-harmonic distortion. In the following section, we discuss the nonidealities of
current-steering DAC and the effects they will cause on both static performance and spectrum specification.
3.1 Finite output impedance of current source
The output impedance of a current-steering DAC consists of the parallel combination of load resistance and total impedance of current sources that are turned on. The output voltage is determined by the current flow through the output resistance. Because the output
impedance is variable due to finite output impedance of the current sources that are turned, the performance of the DAC will degrade [2].
Fig. 3.1 shows a current-steering array including output impedance of each current source. It is a thermometer coded structure, where ro represents the output impedance of each current source. For the thermometer code of height j, the actual output voltage is
, || o
The dependence of the term in parentheses introduces integral nonlinearity (INL). To obtain the INL profile, we pass a straight line through the end points of (3-1) (given by j = 0 and j = N) and find the difference between (3-1) and the line. It is described as follow :
therefore the ideal output voltage for height j is
, || o
The difference between the ideal and actual voltage can result in INL error
After an approximation the INL error can be expressed as
Fig. 3.1 Current Steering Array Including Output Impedance of Each Current Source
Any non-ideal current source has a finite output resistance and can be modeled as shown in Fig. 3.2 [2]. In the figure the current source is terminated over a resistive load at the output. When the different current sources are switched to the output, the total output
resistance is changed and when only static values are considered, the AC current through the load, IL, is
Where Iout is the nominal output current from the DAC, Rout is the output resistance, and RL is the load resistance. From (3.6) it is seen, that if the output resistance of the DAC is
constant, there is only a gain error, which does not degrade linearity. If the output
conductance depends on the input, it will give rise to distortion. Using (3.6) and assuming a signal-dependent output resistance of the DAC, Rout(k), the current delivered to the load is
( ) ( ) ( )
Fig. 3.2 Generalized view of a current source with a non-zero output conductance
Where k is the DAC’s digital input and ρ= RL / Runit. Assume that the input signal is a sinusoidal signal
dc ac sin
k =K +K ⋅ θ + (3.8) v
Where Kdc is the DC level of the signal, is the amplitude of the sinusoid, Kac is the normalized signal frequency times the sequence index, and v corresponds to the quantization error, which is AWGN for converters with a larger number of bits.
Then the output current as given by (3.7) and (3.8) becomes
( ) 1 1
where the noise term v has been neglected. The equation is rewritten as
Examining (3.10) we find that only the second term within parenthesis contains AC frequency information, and we have
The gain factors inside and outside the parentheses can be neglected since we are considering only power ratios when determining the SFDR, and the AC signal is
( )
1Comparing (3.10) with (3.11) it is clear that and will have the same distortion, since they only differ in offset and constant gain. To avoid signal clipping we have that Kac < Kdc for a binary offset code, and we have
Comparing (3.10) with (3.11) it is clear that and will have the same distortion, since they only differ in offset and constant gain. To avoid signal clipping we have that Kac < Kdc for a binary offset code, and we have