Layout

6.1.1 Layout Guidelines for High-Speed Circuits

The layout plan and the block arrangement are critical to the high-speed operation. Based on the iterative process between the layout and the post simulation, the layout guidelines for high-speed circuits are derived. They are listed in the order of benefits to the high-speed operation.

1) Source Coupling

It is the most important guideline to the proposed differential large-swing digital circuits. The sources of differential input transistors should be placed together even at the lack of current sources. These sources are connected by the diffusion layer, but contacts sharing are not recommended.

The source coupling layout relates the differential signals. It can be observed in the post simulation with R-C-CC extraction, even though the phenomenon is not

modeled by the circuits in pre-simulation.

Fig. 6.1: Source-coupling pairs in the delay cell

Fig. 6.1 shows the delay cell of DCDL. Three inverter pairs adopt the source coupling scheme. It improves the 10-Gb/s differential signaling in the delay cell. For the 2.5-GHz domain, the differential signaling also benefits from the source coupling scheme. Fig. 6.2 shows the latch with 3 pairs of NMOS in the source coupling scheme.

Fig. 6.2: Source-coupling pairs in the latch

2) Reducing Capacitive Load

The drain area sharing between two transistors reduces the drain-to-bulk capacitance. Both the drain area sharing and contacts sharing are recommended.

A capacitive load can be partitioned into three components, 1) the area overlap capacitance C , 2) the coupling capacitance _a C , and 3) the fringing capacitance _c C . _f In most cases, the area overlap capacitance C dominates the high-speed _a performance.

i

ib

ob

o

(1) (2)

(3)

i ib

Cb C

O Ob

(1) (2) (3)

Especially it is observed when the drain’s output in the (N+1)th metal layer runs across the power line in the Nth metal layer. It is recommended to use the (N+2)th metal layer and the (N+2)th metal layer for the overlapping.

3) Common-Centroid Geometry

The common-centroid scheme is a general layout guideline. It mainly solves the process variation across the wafer, but it doesn’t do favors to the high-speed circuit operation except that the fully symmetric geometry results in symmetric capacitance, which helps the differential signaling.

For high-speed circuits, the common-centroid guideline is recommended as the global layout guideline, instead of the local optimization. It is verified that all transistors of the delay cell apply a common-centroid scheme, instead of the source coupling scheme, result in a poor performance.

Fig. 6.3: Common-centroid scheme (a) m = 2 (b) m = 3 (c) m = 4

Fig. 6.3 shows the common-centroid scheme for differential signaling. The input transistors are denoted as A, and the input-bar transistors are denoted as B. Assume the I/O direction is either top-to-bottom or right-to-left. The input capacitance of A equals to that of B, and so does the output capacitance.

6.1.2 Grid Design

Fig. 6.4 shows the proposed grid cells for supplies. (a) is the power grid cell. (b) and (c) are the decoupling capacitors filled in the chip’s blank area. Cap1 is a stack type capacitor of 0.17 pF. And Cap2 is a finger type capacitor of 0.7 pF.

The grid design is flexible since all the cells behave like tiles. Metals are self-connected, so supplies are easily transported through the cascaded cells.

A B B A

B A A B

A B

B A

A B A

B A B

(a) (b) (c)

Fig. 6.4: Grid design (a) power grid (b) Cap1 (c) Cap2

6.1.3 Chip Layout

Fig. 6.5: Chip Layout

Table 10: Pads and power configurations

G-S-G-S-G Probe 5 × 3 Vdc, Gdc 60 mW Full 240 mW

Vdd / Gnd 4 × 2 Vdt, Gdt 60 mW Nominal 180 mW

Control 7 Vdt2, Gdt2 60 mW Bypass 120 mW

2.5Gb/s Output 2 × 2 Vdt2, Gdt2 60 mW Debug 180 mW

Pads Configuration Power Configuration Power vs. Modes

(a) (b) (c)

20 um

20 um

40 um

40 um

20 um

20 um

1683 um

994 um

Table 11: Block layout area

Full Chip (pads included) 1683 × 994

Transceiver 700 × 310

Deskew CDR 183 × 149

Area (µm × µm)

The G-S-G-S-G probe pads are used for the high-speed I/O. In Fig. 6.5, there are 3 directions for the 10-G I/O. The data inputs from the left. The clock inputs from the top. The data outputs to the right.

Table 10(b) shows power pads and the corresponding power consumption.

Vdt/Gdt power pair is for the serializer, the clock generator, and DCDL_T. Vdt2/Gdt2 is for the 10-Gb/s output buffer. Vdt3/Gdt3 is for the two 2.5-Gb/s output buffers, while Vdc/Gdc is for the CDR. Each power pair provides 60 mW to the internal circuits. The full-chip power consumption depends on the operation modes, shown in Table 10(c). Table 11 shows the layout area. The transceiver area includes all circuits and 3 pairs of 50-ohm termination resistors.

6.1.4 Core Layout

149um

DCDL FSM

CK 183um

APD Confidence

Counter

PD × 8

(4) DCDL

FSM

ACCU CkBuf

ENC & COMP XOR DoBuf (a)

(3) (2)

(5) (6)

(7)

(c) (1)

(b)

(d)

(a) (b)

Fig. 6.6: Deskew CDR (a) layout (b) block layout with I/O ports

Fig. 6.6(a) shows the layout of the CDR. Fig. 6.6(b) shows the block layout and the signal flow. Table 12 shows the ports information. The global reset at port (d) goes to the FSM and the accumulator ACCU. After each burst-data recovery, it resets the

two up-down counters. DCDL is then re-initialized.

Table 12: The ports information of the CDR (a) internal ports (b) external ports

CC CC

Lead , Lag

COMP COMP

Lead , Lag Internal Ports

(1) DCDL's output Do, Dob (2) Recovered data Q<0,2,4,6>

(3) PD’s output Q<0:7>

(4) XOR’s output Lead<0:3>, Lag<0:3>

(5) Comparator's output (6) Confidence counter's output (7) FSM's output C<0:7>, F<0:3>

External Ports

(a) 10-Gb/s Input Data (b) Global Clock P<0:7>

(c) Recovered Data Do<0:3>

(d) Global Reset

(a) (b)