For temperature verification, Fig. 3.1 gives an overview. On the other hand, concerning local refinement and incremental-kernel application, 3D-AADI owns the feature of executing sec-tional “3D-AADI stamping” (a matrix-establishing process shown in Fig. 5.1) for the updating regions during thermal-aware design iterations. The enhancement, local refinement, and appli-cation, incremental kernel, are discussed as future works on section 5.2.
Since the 3D-AADI method we proposed owns the feature of updating only the affected
Fig. 5.1: An overview of this work (which is in the background-color blocks) and 3D-AADI enhancement. Authors explain the left-middle orange block on section 3.1, the left-down purple block on section 3.2, the right-up gray block on section 3.3, and the right-middle blue block on section 3.4. Besides, the right-middle green sub-flow, which illustrates our 3D-AADI algorithm can be both enhanced in local-refined simulation and applied to thermal-driven kernel into the entire physical design flow, is discussed as future works and applications on section 5.2.
region of the changed grids by sectional “3D-AADI stamping” to the matrix G of Eq.(2.5), this simulator after being enhanced by local refinement and being applied by thermal kernel is both adaptive and incremental. Indeed, it is one of good solution to integrated into physical design flow as thermal-driven kernel due to not only that the node meshing can be non-uniform but also that the data structures of the updated sub-circuits are incremental. For these reasons, the thermal analysis solver can be both a simulator and thermal-aware design kernel. Fig. 5.2 illustrates the local adjustment of grids for satisfying the temperature gradient requirement on the affected region around the updated grids. Pseudo code of local refinement framework is derived in Fig. 5.3.
Fig. 5.2: Local refinement on the affected region around the updated grids for satisfying the requirement.
3D-AADI:Local Refinement Framework Input:
Affected field Output:
New refresh temperature of affected field 01 for Node n = AffectedNodeCount - 1 : 0 do 02 Update and re-slice node of affected field.
03 Construct new node of affected field.
04 Connect neighbors of new node.
05 Update LUVector of affected field.
06 subADILUVectorSolver(UpdateLUVector).
08 end
07 Update temperature of affected field.
Fig. 5.3: Local Refinement Framework.
Chapter 6 Conclusions
3D ICs, which deal with cost-effective achievement by increasing the densities of interconnec-tion between dies, are regarded as an attractive alternative soluinterconnec-tion for overcoming the bottle-necks on 2D planar ICs. In fact, 3D ICs offer the increased system a large number of advantages.
However, one of critical challenges is heat dissipation due to higher accumulated power density and lower thermal conductivity of inter-layer dielectrics for vertical stacking layers of active tier. In this way, the management of thermal issues should be considered during physical design stages rather than only post-packaging verification on the future highly integrated systems. For these reasons, we develop an adaptive thermal simulator applying our 3D-AADI algorithm ac-cording to ADI method to provide temperature distribution during 3D IC physical design flow from floor-plan to verification.
The simulator constructs adaptive size of simulation grids to avoid the limited simulating performance of the most critical position. Furthermore, we apply the concept of ADI iteration method to non-uniform nodes. Eventually, the 3D-AADI tool can be regard as both a reliable thermal simulator and a thermal-driven kernel on 3D IC design flow. The simulator we devel-oped is both adaptive and incremental.
We proposed a thermal simulator on 3D IC applying our 3D-AADI algorithm according to ADI concept to deal with temperature distribution during 3D IC physical design flow from floor-plan to verification. In order to avoid the performance limitation of the most critical po-sition such as hot spots and (thermal or signal) TSVs, this simulator utilizes adaptive analysis size of grids. Furthermore, we develop 3D-AADI algorithm according to the concept of ADI iteration method and analysis the non-uniform meshing calculation and convergence. Finally,
the simulator we developed is both adaptive and incremental, because the 3D-AADI tool can be regard as both a reliable thermal simulator and a thermal-driven kernel on 3D IC design flow from floor-plan to verification.
Bibliography
[1] P.D. Franzon, W.R. Davis, M.B. Steer, S. Lipa, E.C. Oh, T. Thorolfsson, S. Melamed, S. Luniya, T. Doxsee, S. Berkeley, et al. Design and CAD for 3D integrated circuits. In Proceedings of the 45th annual Design Automation Conference, pages 668–673. ACM, 2008.
[2] B. Black, DW Nelson, C. Webb, and N. Samra. 3D processing technology and its impact on iA32 microprocessors. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings, pages 316–318, 2004.
[3] PD Franzon, WR Davis, MB Steer, H. Hao, S. Lipa, S. Luniya, C. Mineo, J. Oh, A. Sule, and T. Thorolfsson. Design for 3D Integration and Applications. In Signals, Systems and Electronics, 2007. ISSSE’07. International Symposium on, pages 263–266, 2007.
[4] S. Im and K. Banerjee. Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs. In International Electron Devices Meeting, pages 727–730.
IEEE; 1998, 2000.
[5] L. Jiang, S. Kolluri, B.J. Rubin, H. Smith, E.G. Colgan, M.R. Scheuermann, J.A. Wakil, A. Deutsch, and J. Gill. Thermal modeling of on-chip interconnects and 3D packaging using EM tools. 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, pages 279–282, 2008.
[6] Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, and Wen-Ching Wu.
Cad reference flow for 3d via-last integrated circuits. In Proceedings of the 2010 confer-ence on Asia South Pacific design automation, pages 187–192. Citeseer, 2010.
[7] J.L. Tsai, C.C.P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.M. Kang, MDF Wong, and SS Sapatnekar. Temperature-aware placement for SOCs. Proceedings of the IEEE, 94(8):1502–1518, 2006.
[8] Y. Zhan and SS Sapatnekar. High-efficiency green function-based thermal simulation algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(9):1661–1675, 2007.
[9] Pei-Yu Huang and Yu-Min Lee. Full-chip thermal analysis for the early design stage via generalized integral transforms. IEEE Transactions on Very Large Scale Integration Systems, 17(5):613–626, May 2009.
[10] T.Y. Wang and C.C.P. Chen. SPICE-compatible thermal simulation with lumped circuit modeling for thermal reliability analysis based on modeling order reduction. In Proceed-ings of the 5th International Symposium on Quality Electronic Design, pages 357–362.
Citeseer, 2004.
[11] P. Li, LT Pileggi, M. Asheghi, and R. Chandra. IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(9):1763–1776, 2006.
[12] T.Y. Wang, Y.M. Lee, and C.C.P. Chen. 3D thermal-ADI: an efficient chip-level tran-sient thermal simulator. In Proceedings of the 2003 international symposium on Physical design, pages 10–17. ACM, 2003.
[13] W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and MR Stan.
HotSpot: A compact thermal modeling methodology for early-stage VLSI design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(5):501–513, 2006.
[14] W. Huang, K. Skadron, S. Gurumurthi, R.J. Ribando, and M.R. Stan. Differentiating the roles of ir measurement and simulation for power and temperature-aware design. In Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on, pages 1–10. IEEE, 2009.
[15] P. Wilkerson, A. Raman, and M. Turowski. Fast, automated thermal simulation of three-dimensional integrated circuits. In Thermal and Thermomechanical Phenomena in Elec-tronic Systems, pages 706–713, 2004.
[16] Y. Yang, Z. Gu, C. Zhu, RP Dick, and L. Shang. ISAC: Integrated space-and-time-adaptive chip-package thermal analysis. IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems, 26(1):86–99, 2007.
[17] J. Cong, G. Luo, J. Wei, and Y. Zhang. Thermal-aware 3d ic placement via transformation.
In Proceedings of the 2007 conference on Asia South Pacific design automation, pages 780–785. Citeseer, 2007.
[18] W. Huang, M.R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusam.
Compact thermal modeling for temperature-aware design. In Proceedings of the 41st annual Design Automation Conference, pages 878–883. ACM, 2004.
[19] M.N. Ozisik. Boundary Value Problems of Heat Conduction. Dover, New York, 1968.
[20] D.W. Peaceman and H.H. Rachford Jr. The numerical solution of parabolic and elliptic differential equations. Journal of the Society for Industrial and Applied Mathematics, pages 28–41, 1955.
[21] J. Douglas and J.E. Gunn. A general formulation of alternating direction methods. Nu-merische Mathematik, 6(1):428–453, 1964.
[22] Y. Saad and Y. Saad. Iterative methods for sparse linear systems. PWS Pub. Co., 1996.