The rest of the paper is organized as follows. We first formulate our concerning problem in Chapter 2. Then we illustrate the overview of the whole 3D-AADI procedures in Chapter 3 and organize it into four parts which are initial heat estimator in section 3.1, adaptive simula-tion grids in secsimula-tion 3.2, uniform meshing construcsimula-tion on 3D-AADI in secsimula-tion 3.3, non-uniform meshing calculation on 3D-AADI in section 3.4. Besides, we discuss local refinement and incremental property in section 5.2 as the applications and future works. In the last chap-ter, we summarize the contributions, provide concluding remarks and analyze the experimental results about our 3D-AADI work.
Chapter 2
Problem Formulation
The geometric information of device location and power dissipation on placement are known as input data. In fact, the input information we need is the material structure and the power distribution, so 3D-AADI thermal simulator can be applied to the stages from partition level to tape-out verification level. This simulator can provide temperature distribution profiles on each simulating tier including the active CMOS layers, interposer layers, and substrate layers.
Since the operating frequency of today’s manufacturing technology node is much faster than the speed of heat dissipation, it is reliable to analyze temperature distribution on steady state [17] [9]. We extract the power library by power simulating tools, considering internal, switching and leakage power as the total power of each device. Based on [18], the heat sink thermal conductance of the primary and secondary heat transfer paths can be modeled as com-ponents and connected with thermal conductance into simulation meshing. Since the ambient air has a constant temperature, the primary and secondary heat sink models respectively connect the bottom and the top terminal with a constant voltage, room temperature node. Fig. 2.1 shows the compact thermal model of N layer 3D IC.
Furthermore, [15] showed the effects of various cooling techniques and indicated that through dummy thermal vias had a very effective cooling influence on temperature dissipation. In this way, TSVs must be considered in 3DIC thermal simulation. For the reason that the routing de-tail of interconnects on the given placement design is not complete, we build each interconnect layer and TSV alignment routing interposer layer into equivalent thermal model based on the weighted summation of each material thermal conductance. As a result of the package struc-tures, the heat-transfer effect of air on vertical surfaces is strictly much less than that of primary
Fig. 2.1: The considering geometry of N layer 3D chip.
and secondary heat sinks on horizontal surfaces. For these reasons, the boundary of four vertical surfaces can be treated as adiabatic [8] [9].
Based on the law of energy conservation, thermal approaches analyze temperature distribu-tion of heat transformadistribu-tion [19] by the following partial differential equadistribu-tions, Eq.(2.1).
ρCp∂T (−→r , t)
∂t = O · [k(−→
r , t)OT (−→r , t)] + g(−→r , t) (2.1)
subject to the thermal boundary conditions
k(−→r , t)∂T (−→r , t)
∂ni + hiT (−→r , t) = fi(−r→si, t), (2.2)
where ρ is the material density, Cpis the mass heat capacity, T (−→r , t) and k(−→r , t) are time- and space- dependent temperature and thermal conductivity of the material, g(−→r , t)is the generat-ing rate of heat source, hi is the heat transfer coefficient on the boundary surface of the chip,
fi(−r→si, t) is an arbitrary function on the boundary surface si, and ∂n∂
i is the differentiation along the outward direction normal to the boundary surface si.
Since we apply the heat-transfer equation to steady-state condition, the left part of Eq.(2.1), which is not variable with time parameter is equal to zero shown on Eq.(2.3). The steady-state heat-transfer equation Eq.(2.4) can be derived as follows.
0 = ∂T (−→r , t)
∂t = 1
ρCpO · [k(−→
r , t)OT (−→r , t)] + 1
ρCpg(−→r , t) (2.3)
− 1
ρCpg(−→r , t) = k
ρCpO · [OT (−→r , t)] (2.4) In order to solve the temperature distribution with finite-difference method and finite-element method, we apply the central-finite-difference approximation and discretize Eq.(2.4) in the spa-tial domain to construct the given design into equivalent thermal conductance circuits shown in Fig. 2.2. After modeling this equivalent circuit, it can be stamped into matrix equation, Eq.(2.5), based on modified nodal analysis (MNA) method. The parameter G is the thermal conductance coefficient of corresponding grid by equivalent weighted summation, parameter t represents the concerning temperature vector of corresponding grids, and p is the heat source vector of corresponding grids.
Fig. 2.2: The thermal circuit model of this numerical thermal simulation on steady state.
Gt = p (2.5)
Chapter 3
The Framework of 3D-AADI Simulator
We approach a both adaptive thermal simulator and integrable thermal-aware kernel on 3D ICs.
It considers three-dimension structure [6] practically and provides the whole 3DIC temperature distribution of steady state. In order to generate the adaptive simulating geometry depending on thermal gradients at the beginning, we utilize the characteristics of heat dissipation as our initial heat estimator. Furthermore, we develop our 3D-AADI algorithm that not only has the property of linear complexity based on the ADI concept but also applies it into non-uniform simulation grids on both construction and calculation. Since we do take incremental application, local refinement, and temperature-aware design into consideration, 3D-AADI algorithm can be applied to local refinement and incremental updating during design iterations. That is to say, this simulator can both provide adaptive temperature distribution profile depending on user-defined or estimator-suggesting granularity, and be suitable to be applied to 3DIC CAD flow.
For temperature verification, Fig. 3.1 gives an overview. At the beginning, simulator parses 3DIC geometry, power library and material files as input information to build heat sources and thermal elements of simulation grids. Then, the first process for 3D-AADI is to provide heat-trend curve as estimator-defined suggestion or to initially discretize the chip into grids of user-given resolution. The second process of 3D-AADI is to establish the adaptive simulating geometry by referring the estimating heat gradients. The third is to construct non-uniform ther-mal circuits, and the fourth is to solve matrices of non-uniform meshing by 3D-AADI algorithm to provide the temperature distribution profiles as output results.
On the other hand, local refinement and incremental-kernel application are discussed as future works on section 5.2.
Fig. 3.1: An overview of this work (which is in the background-color blocks). Authors explain the left-middle orange block on section 3.1, the left-down purple block on section 3.2, the right-up gray block on section 3.3, and the right-middle blue block on section 3.4.
3.1 Initial Heat Estimator
As a quick estimator, we utilize 1D tiles which is composed of the compact thermal model (shown in Fig. 3.2) being our initial temperature estimator to obtain heat estimation. Concerning the accuracy of the compact thermal modeling, there are two reasons that the heat-dissipating in-fluence on vertical is much more obvious than on horizontal. First, the primary heat-dissipating path, including the primary and the secondary heat sinks decided by chip package, is vertical.
Second, the boundary of four vertical surfaces can be treated as adiabatic [8] [9]. However, different estimating resolution causes different error rate. For the reason that 1D thermal model regards lateral heat dissipation as adiabatic between grids, and puts total power on the center of each units, it indicates that the bigger grid-number makes both a larger amount of error due to ignoring more lateral heat transformation and a larger amount heat distributing information of
each grid. On the other hand, smaller grid-number makes both a smaller amount of modeling error due to considering more lateral heat transformation and a larger amount temperature-like information of averaging feature. For these reasons, we can balance the trade-off between heat-distributing information and temperature-like information. In this way, plotting curves shown in Fig. 3.3 indicates us the suitable estimating grid-number resulting from ignoring suitable amount of lateral heat transformation.
Fig. 3.2: The z-tile model of proposed initial estimator.
As soon as the simulator constructs the cell (including TSVs) information of power, material and position, curves (shown in Fig. 3.3 of grid number and heat difference display two parts, the linear region and the saturation region. The linear region for low grid number presents too much average property to concern accurate power distribution. On the other side, the saturation region for high grid number presents too much power distribution to concern lateral heat dissipation.
In order to choose good suggesting resolution, we set criteria by abandoning the extreme and by obtaining enough heat information. On Eq.(3.1), we choose the integer level whose average-heat-difference changing rate is stable than its previous level,so we find the integer i such that average-heat-difference changing rate of leveli is very close to that of leveli+1.
Fig. 3.3: The z-tile curves built by initial heat estimator for test chip 1 (on left one) and test chip 2 (on right one). The x-scale presents planer grid number which is gridxby gridy of every simulating z-tier. The y-scale presents the average of heat difference comparing with average temperature of the entire chip.
1 < (AvgErri− AvgErri−1)/AvgErri−1
(AvgErri+1− AvgErri)/AvgErri < 1 + ε (3.1)
where AvgErri is the average of heat difference of i resolution reference by comparing with chip average temperature, ε is a small and positive real number. Then, we divide the whole chip into grids of suggesting level, which can be user-given beforehand or estimator-defined by Eq.(5.1). In this way, the initial estimator applying 1D z-tile method for obtaining the trend of thermal dissipation is reliable to be the reference approximation on proper simulating grid size.