Loop Analysis

Fig. 18. Small-signal model of the AC ripple control buck converter.

Fig. 18 shows the small-signal model of the dual modulation buck converter with the AC ripple detector [23]. The loop gain can be divided into two parts. The first part, which is the power stage, contributes duty-to-output transfer function and contains dual poles due to the output LC filter as expressed in (18) with a DC gain of Gvd0.

 

The zero, ωesr, generated by Resr is pushed to high frequencies by using small ESR. RL

is the loading resistor and Rs is the series resistor of the LC resonant loop, which is the sum of MOSFET on resistance, inductor resistance, and Resr.

The second part, composed of the controller, contributes the output-to-duty transfer function. In dual modulation, the control path contains two feedback loops, namely, the primary loop and the secondary feedback loops. The primary feedback loop is determined by the AC ripple detector and the error amplifier. Thus, the primary duty cycle can be decided through the signals, vs and vEA, by the PWM comparator. On the other hand, the secondary feedback loop is determined by the error amplifier and the secondary modulator.

The loop selection is determined by the LPD circuit. At very light loads, only the secondary modulator loop is selected as the feedback path. The feedback signal directly passes through the secondary modulator loop, ASEC(s), to generate the duty cycle. As load current increases continuously, the feedback signal passes through both primary and secondary loops. Thus, dual modulation combines the primary and the secondary modulators at medium to light loads. At heavy loads, the feedback path is decided by the primary modulator when load current is larger than Iload(threshold). The feedback signal only passes through the primary loop since the secondary loop ASEC(s) is disabled and the switch is always connected to the primary path.

The transfer function, APRI(s), of the error amplifier with the PI compensator can be

derived as (19).

The DC gain is constituted by the error amplifier’s transconductance, Gm, and the output resistance, Ro. The PI compensator introduces one pole, ωPI_p composed of Ro and compensation capacitor Cc, and one zero, ωPI_z composed of the compensation network, Rc

and Cc.

Similarly, the transfer function, ASEC(s) as shown in (20) contributed by the secondary modulator, is used to provide a low-bandwidth response to filter out the high-switching PWM signal according to the load current. Thus, the DC gain of the ASEC(s) is inversely proportional to the load current and controlled by Iload(threshold).

 

load threshold load

The close-loop transfer function in the secondary modulator can be expressed as (21).

       

SEC vd PRI SEC

T s  k G s A s A s (21)

Therefore, the close-loop transfer function in dual modulation can be expressed as (22).

As the load decreases continuously, the contribution of the primary modulation becomes smaller than that of the secondary modulation. At very light loads, the secondary

modulator can take over the control authority.

In this study, the primary modulation is demonstrated as follows: The control duty can be expressed as (23) to include the results from the AC ripple detector and the error amplifier.

Owing to the LC double poles, the AC ripple detector as a differentiator can introduce a low-frequency zero, ωAC, with a time constant, CdRd, to increase the system stability. Thus, the transfer function, BAC(s), is shown in (24).

 

AC d d

AC

B s s sC R

  

In a steady state, the PWM comparator transfer functions Fm1 and Fm2 have the same value of Fm as defined in (25).

1 2

m m m

F  F  F (25)

Thus, the output-to-duty transfer function can be derived as shown in (26). As expressed in (27), the system contains one single, low-frequency dominant pole, ωPI_p, and two compensated zeros, ωzcomp1,2.

   

As a result, the close-loop transfer function can be expressed in (28), which contains two zeros and three poles. According to design parameters shown in Table V, the position of the three poles and the two zeros can guarantee system stability during the primary PWM

operation.

Table V: Design parameters of the proposed converter.

EA’s G_m 62.5 μA/V

Fig. 19 depicts the analytic Bode plot of the primary modulator with the AC ripple detector. Expectedly, the phase margin is larger than 45 degrees since the pole-zero cancellation of the proposed AC ripple detection technique is achieved without using a large ESR.

Fig. 19. Bode plot of the proposed converter system.

Chapter 4

Circuit Implementation

The architecture of the proposed buck converter has illustrated in Fig. 16. The converter is composed of a power stage, a feedback network, and the control stage including primary modulator and secondary modulator. The power stage contains a pair of power switches SWP and SWN, and an inductor L. Owing to high switching frequency, compact off chip inductor and filtering capacitor CO can be used. Output voltage VOUT is scaled down to VFB by the voltage divider, composed of resistors RFB1 and RFB2. The controller stage is utilized to turn on/off power switches SWP and SWN.

In normal operation, the primary modulator produces the original PWM pulse to regulate output voltage. The comparator CMP compares the output signal VEA generated from the error amplifier EA, with the summation of the sensing signal VS and the slope compensation signal VSAW to decide system duty.

In light load condition, the secondary modulator generates the HFM pulse to combine with original PWM pulse. The LPD circuit generates VLoad, which stands for the load condition, VLoad is combined with the error signal VEA to generate input control signal of HFM circuit, VCtrl, and HFM circuit produces the optimal HFM pulse (VHOP) to modulate with original PWM pulse (VPRI), the modulated control signal (VGATE) can reduce the switching times of power switches to reduce the switching loss.

Furthermore, the primary modulator will shut down automatically in very light load or no load condition, and the secondary modulator can regulate the output voltage by itself to save much more efficiency.

The operation of the whole system is mentioned above. The operations of key sub-circuits in the control stage are explained in the following sections.