Although switching converters have high conversion efficiency, but the power loss will increase and result in efficiency reduction at different load conditions. The power consumptions can be classified with three parts. The first is the power losses due to large current pass through the equivalent resistance of the power MOSFET, the equivalent resistance can be expressed as RON, this power consumption is named conduction loss (PCON) and expressed as follow.
2 CON OUT ON
P I R (4)
The second part is the charging and discharging alternately at large gate parasitic capacitor of the power MOSFET when the switching on and off periodically. This is a large loss of converters at light load condition named switching loss (PSW) and expressed as follow.
( ) 2
SW GP GN IN SW
P C C V f (5)
The CGP and CGN are represented as gate parasitic capacitors of power PMOSFET and NMOSFET, VIN is represented as input voltage, and fSW is represented as switching
frequency. The third is the quiescent current of converter’s internal controller to regulate output voltage at no load, it’s also called idle mode. This power consumption is named system power loss (PSYS) and defined the multiplication of quiescent current and input voltage. That is to say, the power conversion efficiency of DC-DC converters can be defined the ratio of the output power and the total input power, and is expressed as follow.
As above mentioned, the conduction loss (PCON) is dominated at heavy load because of large output current flowing through the power MOSFETs. Contrarily, switching loss (PSW) and system loss (PSYS) are dominated at light load condition because of slight output current.
So how to maintain high efficiency at wide load range is an important issue.
There are three most basic controlling methods named pulse width modulation (PWM), pulse frequency modulation (PFM), and hysteretic control technique. The following sections will introduce these controlling methods, respectively.
2.2.1 Pulse Width Modulation (PWM)
In PWM control operating, the power MOSFETs are controlled by a constant clock cycle, the PWM control waveforms are shown in Fig. 8 [15] [16]. While the ramp signal is lower than the control signal, the PWM signal at high level; contrarily, when the ramp signal is higher than the control signal, the PWM signal changes to low level. The main modulation is change the width of every clock cycle by the control signal and the output voltage is determined by the duty ratio of the PWM signal.
The conduction loss and switching loss are focused in PWM control operation. The summation of these two power loss is expressed as follows.
2 ( ) 2
CON SW OUT ON GP GN IN SW
P P I R C C V f (7)
As shown in Eq. (5), the switching frequency is constant but output current varies with different loads. That is to say, the conduction loss maintains fixed but the switching loss is variable with loads. The summation of conduction loss and switching loss at different load can be shown in Fig. 9.
Fig. 8. Waveforms of pulse width modulation.
Fig. 9. Combination of conduction loss and switching loss in PWM control.
2.2.2 Pulse Frequency Modulation (PFM)
In PFM control operating, power MOSFETs are controlled by a vary frequency, the control waveforms are shown in Fig. 10 [17]. The on-time is fixed and off-time is variable determined by different loads in PFM control. By controlling the off-time of each switching cycle, the desired output voltage can be obtained. Therefore, the smaller output load could make switching frequency reduced.
The summation of conduction loss and switching loss in PFM control is the same with Eq. (5). In PFM control operating, vary switching frequency with different load conditions makes the switching loss reduced at light load, the diagram is shown in Fig. 11.
Fig. 10. Control signal waveforms of pulse frequency modulation.
Fig. 11. Combination of conduction loss and switching loss in PFM control.
2.2.3 Hysteretic Control Technique
The hysteretic control structure is shown in Fig. 12 [18], the main control method is generating a hysteresis window. By controlling the upper and lower boundary to regulate the output voltage, when the feedback voltage touch to the hysteretic upper boundary, the power NMOSFET will turn on and PMOSFET will turn off to make the inductor current discharged and feedback voltage will decrease. At the same time, the hysteretic window will change to the lower boundary. While the feedback voltage touch to the hysteretic lower boundary, the power PMOSFET will turn on and the power NMOSFET will turn off to make the inductor current charged and feedback voltage will increase. The hysteretic window which is calculating by superposition theorem can be expressed as follows.
2 1 2
The features of hysteretic controller are described as follows; firstly, the main control
circuit is comparator, so there is no compensation issue without error amplifier. Secondly, without using any clock generator, the switching frequency of hysteretic controller is generated by system itself. The following is the calculation of feedback voltage variation, as expressed as follows.
The voltage VFBAVG is the average voltage of feedback, ideally is DVIN, the parameter D, is the duty ratio of the buck converter. Because the hysteresis window variation (VH) equals to feedback voltage variation (△VFB). Combining the Eq. (8) and Eq. (9), the switching frequency can as expressed as follows.
1 0
By controlling the resistor R, capacitor C and the ratio of resistors R1 and R2 can define the switching frequency, which is very suitable for high switching frequency design. Finally, because the output ripple has been defined, it can’t choose the low ESR capacitor to reduce output ripple.
Fig. 12. The structure of hysteretic control technique.