The chip manufactured using TSMC 0.25-µm CMOS process suffers from the problem of ESD severely. The gate oxide breaks down easily with inexact operation procedure and without protection circuits. We should give voltage on the gate of PMOS first then increasing voltage on the source side gradually, conversely, give voltage on the source of NMOS first then increasing gate side gradually when turn on the bias circuits. Besides, for decreasing the circuits damaged by pulse, we should add protection circuits at each gate side of biasing circuits as Fig. 3.13 shows.
Fig. 3.13 Protection circuit
The power lines of the testing circuits are also a critical topic to the performance of measurement. Digital or analog power supply is noisy power source, so we add bypass capacitors from 1uF, 1nF, to1pF as near the pad of chip as possible to suppress the noise coming from power source. Besides, adding more via between the top and bottom of the test board and using GSG layout on the power lines and bias lines all can help get more stable bias. Fig.
3.14 shows the testing board with and without the stability equipment.
(a) Testing board before (b) Testing board after modification Fig. 3.14 Measuring board
3.15(b) measures the phase noise which is even -88dBC/Hz, -14dB worse than with pure power source.
Fig. 3.15 (a) Spectrum of frequency synthesizer without bypass capacitor
Fig. 3.15 (b) Phase noise of frequency synthesizer without bypass capacitor
The measuring phase error of quadrature phase is 20° worse than simulation. After analysis, we find the bond wire from the pad to the testing board will induce much phase shift and influence the measuring result. If we assume the chip inside and line of testing board all match to 50 Ω, using Microwave office tool to simulate the length of bond wire with 1µm variation shows that there will be 7° phase difference caused bond wire as Fig. 3.16 shows. Besides, the bond wire causes unbalance LO power in port1 and port4.
There is approximately 28° phase error if the power difference between two
quadrature generator is only -20dB at 2.4GHz which will have some power leakages from port1 to port4, reversely from port4 to port1 and degrade the ability of image cancellation. Moreover, the testing board actually is difficult to match to 50Ω for bond wire consideration. After we calibrate the phase error due to the LO input power difference which is approximate 0.4dB, bond wire length variation which is roughly 1µm, quadrature generator phase error which is about 2°, the phase error can be less than 1° in really. So, the best way to get the accurate phase error is to design a mixer circuit inside of the chip to down convert the frequency to lower frequency to reduce the bond wire effect.
(a) Bond wire effect simulation (b) Phase error of S21
Fig. 3.16 Phase error simulation
When measuring the settling time of frequency synthesizer, we try to use arbitrary element values of loop filter to see the impact on the settling time.
Fig. 3.17 shows the settling time compared with simulation using arbitrary element values as listed in table 3.3. The result points out that the settling time may be larger than 200µsec if using unsuitable filter values. Besides, using too long wire connecting to the VCTR will make the settling time longer than
200µsec, too.
Element value of loop filter
C1 47pF
C2 470pF
R1 15kΩ
C3 47pF
R2 15kΩ
Table.3.3 Loop filter elements
(a) Measured settling time (b) Simulated settling time Fig. 3.17 The settling time using arbitrary loop filter values
Chapter 4
Sub-harmonic Mixer
4.1 Architectures
In this chapter, we give the approach to the even-harmonic mixer, present our analysis, and show its post simulation performance. Finally, we compare the even-harmonic mixer with the traditional Gilbert cell mixer.
4.2 Sub-Harmonic Mixer Core Circuit
Fig 4.1(a) shows the traditional Gilbert cell mixer which can be divided into two part where M1、M2 are as RF signal amplifier and they also can increase the LO to RF signal isolation ; M3-M6 is the actual frequency mixing part. The even-harmonic mixer is modified from Gilbert cell mixer which only replaces mixing mode MOS to differential pair as fig. 4.1(b) shows [5]. The CMOS even-harmonic mixer provides down conversion mixing of the differential RF input signal with even harmonic of the LO differential signal while suppressing RF mixing with the LO fundamental and odd harmonics.
As shown, suppression of odd harmonic mixing is accomplished by summing
the differential signals at the drains of M3、M4, M5、M6, M7、M8, and M9、
M10. The quadrature ~ FRF/2 signal applied to the LO inputs also allows the RF signal to be switched on every quarter cycle of the LO drive waveform,
creating an effective 2*Flo signal. The inductor L1 is used to produce a pole at 5GHz to increase mixer conversion gain and L2 L3 is for RF input matching.
(a)Traditional Gilbert Cell Mixer (b) Sub-Harmonic Mixer Fig. 4.1 The schematic of Gilbert Cell Mixer and Sub-Harmonic Mixer
4.3 Quadrature Phase Generator
For measurement consideration, we use poly-phase filter to generate quadrature phase for LO input [15]. A simplified schematic of the poly-phase filter is shown in Fig. 4.2. The poly-phase filter outputs phase and amplitude
bandwidth. We can use 2-ord poly-phase filter to increase circuit bandwidth.
However, this will decrease the LO signal power further.
Fig. 4.2 Poly-phase filter circuit
4.4 Simulation Result of Sub-Harmonic Mixer
The even harmonic mixer has been fabricated using TSMC 0.25-µm mixed-signal CMOS process. The final layout of fully integrated Mixer is shown in Fig. 4.3.
Fig. 4.3 Layout of even harmonic mixer
All elements are fully integrated on a chip including spiral inductors, metal-insulator-metal (MIM) capacitors, multi-finger RF NMOS transistors, poly resistors and decouple MOS capacitors. The total chip size including the pads is about 850umx850um. At high frequencies, the drain and source of a MOSFET, pads, inductors, and other element on the Silicon (Si) substrate have resistive components due to resistivity of the Si substrate. These parasitic resistances consume signal power, generate thermal noise, and thus noise performance of the mixer is degraded a lot. To avoid these effects from pads, we use shielding PAD at RF、LO input and IF output to reduce coupling noise from the noisy Si substrate. [16]
Fig. 4.4 shows the simulation output waveform of mixer. The high frequency component can be removed by off-chip filter.
Fig. 4.5 shows the result of mixer conversion gain versus RF input frequency with the LO input frequency from 2.5GHz to 2.7GHz and an LO input power of 3dBm and IF frequency of 20MHz is selected. A two tone test is performed to measure the input third order inter-modulation point of the mixer. The two tones are at 5.2GHz and 5.205GHz resulting in fundamental tones at 20MHz and 25MHz , and third order intermods at 15MHz and 30MHz at the IF output.
Fig. 4.5 RF input frequency versus conversion gain
Fig. 4.6 shows the fundamental and intermod powers with respect to the two tone input powers. Extrapolation of the two curves results in an IIP3 of -4dBm.The mixer has a simulated double sideband noise figure of 14dB at an RF frequency of 5.25GHz with the LO input power of 3dBm and IF frequency of 20MHz. Fig. 4.7 shows the mixer double sideband noise figure. Table 4.1 summarizes the post simulation performance.
Fig. 4.6 Two tone test of IIP3
Fig. 4.7 Double sideband noise figure
Power Supply 2.5V RF input frequency 5.25GHz
IIP3 -4dBm P-1dB -13dBm Mixer Core power 5mW
Table 4.1 : Performance Summary
4.5 Comparison to Fundamental Mixer
Careful examination of Fig. 4.1(b) will shows that the even harmonic mixer(IF=RF-2*LO) can be converted to a fundamental mixer (IF=RF-LO) by connecting the 0oand 180 LO inputs together ,and also the 90 and 270 LO inputs together. The result is a fundamental LO Gilbert cell mixer whose input stage is identical to the even harmonic mixer. Table 4.2 shows the comparison of the even harmonic mixer to the fundamental mixer. The simulated NF for fundamental mixer is about 3dB lower than the even harmonic mixer and conversion gain is about 5dB higher than it.
Parameter Even Harm. Fundamental Conversion
Table 4.2: Comparison of sub-harmonic mixer to fundamental mixer
Chapter 5
C ONCLUSIONS A ND F UTURE P ROSPECTS
5.1 Conclusions
A fully integrated 2.4GHz CMOS frequency synthesizer is demonstrated.
Table 5.1 lists the measurement data compared to the spec of Bluetooth requires. The data shows that we achieve the spec requirement of Bluetooth except to phase error. However, this design suffered from strong spurious tones, and consumed large power in VCO buffer.
Measurement Spec of Bluetooth
Power supply 2.5V N.A
Tuning range of VCO 2.392 ~ 2.514GHz 2.4~2.481GHz Phase noise -102dBc/Hz@1MHz -120dBc/Hz@3MHz
Spurious tones -40dB N.A
Table. 5.1 Measurement data compared to spec requirement
5.2 Future Prospects
There’re several directions for future work. First, a more accurate method must be set to measure the phase error. We should integrate the down conversion mixer to convert the LO signal to lower frequency for decreasing the bond wire effect to the measurement of phase error. Second, the spurious tones are strong and seriously influence the signal. We have some tactics to alleviate this problem, narrow the bandwidth of the loop filter or minimize the interference of crystal oscillator by designing a current matching circuit in Charge Pump. Through the above two ways, spurious tones can be suppressed more effectively. Third, the VCO buffer should be re-designed to lessen power consumption and counterwork process variation.
Besides, the architecture of conventional integer-N frequency synthesizer suffers from many draw back. The limited bandwidth of integer-N frequency synthesizer causes out off band noise from VCO. Large divide number intensifies the in-band noise from the reference and phase detector noises. The architecture of fractional-N frequency synthesizer solves the problems above.
Moreover, the settling time can be faster by using fractional-N frequency synthesizer [20]. Therefore, the future research should be focused on the architecture of fractional-N frequency synthesizer.
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