Chapter 1 INTRODUCTION
1.2 Thesis organization
This thesis constructs a fully integrated 2.4GHz frequency synthesizer and a 5GHz sub-harmonic mixer by TSMC CMOS 0.25-µm technology.
Chapter 2 introduces synthesizers’ architectures, simulation information, system bandwidth considerations and designing tips.
Chapter 3 presents the measurement results of each building block of the frequency synthesizer, and of course the measured data of whole system.
Fig. 1.2 Down/up conversion of signal
Finally, we discuss our measurement results, self-criticisms of the shortcomings in specifications, and future prospects in Chapter 5.
Chapter 2
F REQUENCY S YNTHESIZER
2.1 Architectures
In this chapter, we discuss about all the functional blocks in integer-N frequency synthesizer and how to design them. Fig 2.1 presents the architecture of integer-N frequency synthesizer. The frequency synthesizer contains five functional blocks, including voltage controlled oscillator(VCO), divider, phase frequency detector(PFD), charge pump and low pass loop filter(LPF). Except the reference oscillator and LPF, all blocks are done on chip.
We separate the power supplies of all the blocks in order to avoid substrate cross talk and for testing consideration [8]. We will discuss how to design all functional blocks latter.
Fig. 2.1 The architecture of integer-N frequency synthesizers
2.2 VCO Design
2.2.1 Design Issues and Introduction
VCO is the core circuit in the frequency synthesizer. In most RF design, we use LC-tank oscillator instead of ring oscillator for better phase noise. For image cancellation, we hope VCO can provide quadrature phase output signal. There are three ways to generate quadrature signals: divide-by-two circuit [9]; RC-polyphase network [1]; and two VCOs cross connect with each other [10]. Using divide-by-two circuit needs to design a VCO operate at the double frequency of original frequency. VCO operating at higher frequency will consume more power and have poor phase noise. Besides, this structure also shows poor quadrature accuracy because of the requirement of 50% duty cycle VCO. A VCO with RC-polyphase network consumes less power than others, but RC-polyphase is signal power hungry. Besides, the bandwidth of RC-polyphase is too small to cover the band from 2400MHz to 2481MHz.
Based on the former reasons, we choose two VCOs cross connect with each other here to generate quadrature signal which have accurate quadrature phase signal and large output signal power. The whole schematic of the quadrature VCO is shown in Fig. 2.2(a). The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors to enhance negative conductance and LC-Resonator to conclude the resonance frequency. Four inverters cascade to create quadrature phase output as Fig. 2.2(b) shows.
Fig. 2.2(a) Quadrature phase VCO schematic
Fig. 2.2 (b) Four inverters cascade to generate quadrature phase
When designing the frequency range of VCO, large tuning range enhances the sensitivity of VCO to substrate noise. However, small tuning range is hard to cover the band of Bluetooth from 2.4~2.483GHz. In order to guarantee the whole tuning range of implemented VCO is exactly as we require, we add capacitor banks at the two ends of LC-tank. This can help us to adjust the tuning range of the implemented chip.
This design adopts 3 sets of capacitor bank, i.e. there’s three control bits and enables us to set the oscillator under 6 operating conditions: 000, 001, 010, 011, 100, 101, and 111. Different control bit is connected to different amount of parallel capacitors; higher bit is connected to a larger capacitance. When a control bit of capacitor bank is at high level, the capacitor is enabled and the capacitance of LC-tank is increased.
Bank design gives a stronger guarantee to avoid the shifting of oscillating frequency, however, it worsen the phase noise of VCO due to the turn on
resistance of switch MOS [1].
2.2.2 Simulation Results of VCO
The simulated output transient waveform of VCO is shown as Fig. 2.3. In the design, the phase error is almost zero if no device mismatches. Fig. 2.4 shows the tuning range of the VCO at bank 100 is approximately linear from frequency 2.4~2.483GHz which implies a constant KVCO in the operation range;
it is an advantage for phase-locked loop. Fig. 2.5 shows the simulated phase noise at oscillation frequency 2.448GHz. At 3MHz offset from the carrier, phase noise is -120dBc/Hz. This specification satisfies Bluetooth standard.
Fig. 2.3 Simulated output transient waveform
90°
0° 180° 270°
2.35 2.37 2.39 2.41 2.43 2.45 2.47 2.49 2.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
control voltage(V)
osc illatio n frequency(GHz)
Fig. 2.4 Simulated tuning curve
Fig. 2.5 Simulated phase noise at oscillation frequency 2.448GHz
2.3 Fully Programmable Frequency Multi-Modulus Divider
2.3.1 Design Issues and Introduction
Fig. 2.6(a) Traditional prescaler and Program, Swallow counter
frequency divider. However, the extendibility of this architecture is low for having to determine the divide number of P-counter and S-counter for different range of divider. Fig. 2.6(b) presents another architecture which we adopt in this work [16]. It is composed by 11 cascaded dual modulus asynchronous divide-by-2/3 circuits. This architecture only requires change the number of divide-by-2/3 block for different range of divider. This design assures only the first two stages of the divider operate at the frequency over GHz. We can set divide modulus N by changing the input level of each program bits (b0, b1, b2…). In this work, divider can be programmed to all
Frequency divider is a critical part besides VCO due to its high operating speed. The maximum operating frequency is limited by the parasitic capacitance of the layout connection path and the load of the first stage to the second one. In order to reach a maximum operating frequency at 2.5GHz, the first two stages are realized in a differential Source Coupled Logic (SCL) and we scale down the NMOS transistor size of the second stage to minimize the first stage’s capacitor load. Carefully choosing the transistor sizes and accurately counting the parasitic capacitor are all critical to the correct operation of divider. Fig 2.7 is the SCL circuit which works as a high speed NAND-DFF.
The following 9 stages are realized with digital cells which can operate at frequency up to several hundred MHz and consume less power than the first
two stages.
Fig. 2.7 Differential source coupled logic
2.3.2 Simulation Results of Divider
Simulating 11 stages of dual modulus asynchronous divide-by-2/3 circuit takes long time. So we first take the first five stages to simulate. Fig. 2.8 shows the simulation result of divide by 31. We see the input clock even with 0.25 V peak to peak swing and frequency up to 2.6GHz still working well.
CLKp CLKm
Fig. 2.8 Frequency divider simulate divide by 31 output waveform
The co-simulation result of fully programmable frequency multi-modulus divider and VCO is as shown in Fig. 2.9. The VCO output frequency is set at 2448MHz and the divide modulus is set at 2448, too. We can obviously observe the period of output divided signal is 1µs, this figures out our divider is working regularly.
1µs
Fig. 2.9 Frequency divider simulated with VCO
2.4 Phase/Frequency Detector
Phase frequency detector can detect both phase and frequency difference between the reference signal and the output signal of the frequency divider. As shown in Fig. 2.10, if the frequency of input A is greater than that of B, QA is high, but QB is still low. On the contrary, if the frequency of input B is greater than that of A, QB is high, but QA is still low. If the frequency of A equals that of B, the circuit will check the phase difference between the two inputs and generate a pulse that equals the phase difference at QA or QB.
Fig. 2.10 (a) PFD block diagram
Fig. 2.10 (b) PFD state diagram
Fig. 2.10 (c) PFD timing diagram
In the thesis, we choose three state phase/frequency detector (PFD) for detecting both phase and frequency difference. Fig 2.11(a) shows the conventional circuit of three state PFD circuit. The circuit consists of two D-flip flops and an AND gate. We set the initial condition of the two D-flip flops’ output QA=QB=0. If B=0 but A is from 0 to 1, then QA=1 until B is also from 0 to 1 which makes QB becomes high and resets the two D-flip flops to low. The PFD’s characteristic is ideally linear for the entire range of input phase differences from -2π to 2π as Fig. 2.12 shows. When the inputs differ in frequency, the phase difference changes each cycle by 2π((TCKref
-TCKout)/max(TCKout,TCKref)). On every clock cycle during frequency acquisition, the phase differences steps across the PFD transfer curve from 0 to ±2π and repeats as the output clock cycle slips. So the control voltage of VCO is pumped monotonically toward that of the desired frequency.
However, the conventional PFD circuit has the drawback of dead zone existed when it incorporates with charge pump. The dead zone generates phase jitter since the control system does not change the control voltage when the phase error is within the dead zone as Fig2.13 shows. Fig. 2.11(b) shows
the PFD realized in this thesis. The delay inverter chain used in the circuit which increases the delay of reset signal can eliminate dead zone [12].
Fig. 2.11(a) Conventional PFD circuit
Fig. 2.11 (b) Modified PFD without dead zone
IP
∆θ π
− 2 2π 4π
π
− 4
Fig. 2.12 PFD characteristic
Fig. 2.13 Limitation caused by dead zone
2.5 Charge Pump
The charge pump [11] (Fig. 2.14) adopted in this thesis works with a fixed reference current. To achieve a high voltage output range at the charge pump, the transistor size of the current mirror transistors (M1-M11) must be chosen carefully. Also an accurate layout of the charge pump is important to improve the matching of the positive and negative current to avoid mismatch currents.
Mismatch currents produced when the two phase are compared cause reference spur. Reference spur interferes with adjacent channel in RF receiver and it also produces undesired spectral emission in RF transmitter. We implement two additional transistors (M12, M14) to guarantee in case of switching the transistors M13 and M15, their sources are already precharged.
Above reduces current peaks during the switching time and suppressing the spurious tones, too.
2.6 Loop Filter and Loop Bandwidth Considerations
The characteristic of PLL helps frequency synthesizers partially alleviate their phase noise contributed by VCO. Extending the bandwidth of PLL can reduce phase noise in band of the loop and increase the settling time of the whole loop. However, a wide band PLL suffers from higher level of spurious tones. The loop filter can determine the bandwidth of PLL by introducing poles and zeros in the close phase locked loop. The poles help degrade the magnitude of reference spur and the zeros help PLL have enough phase margin to guarantee the close loop’s stability.
Fig 2.15 shows the linear model of PLL, the transfer function is:
Fig. 2.15 Linear model of PLL
We use 3rd order passive loop filter in this design. Fig. 2.16 shows a standard third order loop filter used in most synthesizers. The filter comprises a second order filter section and an R2 and C3 section to provide an extra pole to assist the attenuation of the side bands at multiples of the comparison frequency that may appear. However, extra pole may make the whole loop unstable. So, the design of loop filter is critical.
Fig. 2.16 Third order loop filter
The element value of loop filter can be determined on the following step [13].
First, we have to choose the loop bandwidth of PLL. The locking time of the
of the loop bandwidth, are
From equation 2.3, the estimated comparison frequency is ≧500kHz. Our reference frequency is 1MHz which satisfies the requirement. Equation 2.4 predicts an estimated loop bandwidth≧25kHz in order to achieve lock in time.
N
Based on above equations, we can obtain a set of element values. Besides, we can get another set of element values from the loop filter simulation tool shown in Fig. 2.17. The values are all listed in Table 2.1：
The two set element values slightly differ because the hand calculate do
some approximation when analysis. We will see the approximation will not have much influence on the settling time of whole circuit in section 2.7.
Fig. 2.17 PLL loop filter design software
Calculated Result Simulated Result
C1 5pF 6.5pF
C2 60pF 138pF
R1 212kΩ 139kΩ
C3 1pF 0.6pF
R2 636kΩ 740kΩ
Table 2.1 Loop filter elements
2.7 Simulation results of whole frequency synthesizer
Finally, all the building blocks mentioned in previous sections and chapter are combined to be a whole frequency synthesizer and simulated together as Fig. 2.18 shows. Because frequency synthesizer circuit contains many sub-circuits, simulating the settling time from circuit level takes a lot of time. So at first, we use ADS tool to perform behavioral simulation of frequency synthesizer’s settling time and then use eldoRF to verify whether the connections of whole loop are correct or not.
Fig. 2.18 Frequency synthesizer building blocks
We use different element values of loop filter derived from above section to simulate and the outcome in Fig. 2.19 shows the settling time is less than 200µs as the spec of Bluetooth required. Fig. 2.20 shows the close loop spectrum of VCO.
Fig. 2.19(a) Locking transient simulation element values of loop filter from hand calculation(2448MHz)
tool(2448MHz)
Fig. 2.20 Locking spectrum simulation (2480MHz)
Fig. 2.21 and 2.22 show the layout and the die photo of whole chip. The die size is 1400µm×950µm.
2480MHz
Fig. 2.21 Whole frequency synthesizer layout
Fig. 2.22 Whole chip die photo
1400µm
950µm
C HAPTER 3
M EASUREMENT R ESULTS
3.1 Measurement Considerations
This work is measured on PCB, the measurement instruments include 8563E spectrum analyzer and 54602A oscilloscope as Fig 3.1 shows.
(a) 8563E spectrum analyzer (b) 54602A oscilloscope
(c ) E3611A power supply Fig. 3.1 Measurement instruments
Fig. 3.2 shows the PCB layout and the testing board of the chip. The chip is stuck on testing PCB, and wires are bonded from the pad on chip to feed bias voltages. We use a DIP switch to switch the VCO capacitor Bank and divider. An off-chip 1MHz oscillator instead of function generator is used to produce reference clock for suppressing the noise coming from reference frequency. The loop filter is also designed out of chip for easily modifying element values and decrease chip area although it introduces more noise than designed fully on chip.
Fig. 3.2 PCB layout
Fig. 3.3 Testing board
3.2 VCO Measurement Results
The measured spectrum and tuning range of VCO used in this work is shown from Fig. 3.4 to Fig. 3.5. The tuning range of Bank(100) covers the band from 2.4GHz to 2.483GHz as we desire. Fig. 3.6 shows the tuning range of measurement data compared with simulation results. The chips are discovered falling on SF corner from WAT data provided by TSMC, so we re-simulation with this condition.
The measured tuning range is 2.392 ~ 2.514GHz, comparing with our simulation results which is 2.288~2.411GHz at TT corner and 2.343~2.478GHz at SF corner. There are approximately 40~50MHz frequency differences
between measurement and simulation. That means the parasitic effects are evaluated more than reality. With careful examination, we find the parasitic capacitor of RFMOS has been evaluated twice. Besides, the frequency using two VCO connected to each other is more sensitive to corner variation than that only using one VCO.
Fig. 3.4 The open loop Spectrum of frequency synthesizer
Fig. 3.5 Measured tuning range of VCO under different bank conditions
Fig. 3.6 Measured tuning range of VCO compared with simulation
After re-simulating the tuning range with reducing the parasitic capacitor of VCO resulting from RFMOS, we can get better fit of the measurement data with simulation results as Fig. 3.7 shows.
Fig. 3.7 Measured tuning range of VCO compared with re-simulation
We use quadrature generator to measure the phase error of VCO output signal. Fig. 3.8 shows the layout of quadrature generator. The s-matrix of quadrature generator is [14]:
(3.1)
(a)The layout of quadrature generator (b)The layout of whole circuit Fig. 3.8 The layout circuit for quadrature phase measurement
When the phase of input signal of port 1 is θ˚ and port 4 is ψ˚, port1 port2 having phase difference roughly 90˚, we can get the s-parameter of port2 and port3 as formulation from 3.2 to 3.4 presents.
Port2=
The measurement shows the output power of port2 is -25dBm and the output power of port3 is -10dBm. From formula 3.4, we can deduce the phase error between port2 and port3 is 20˚.
3.3 Whole Circuit Measurement Results
The measurement data of whole synthesizer are shown in following figures. Fig. 3.9 are the output spectrum when synthesizer are locked at 2400, 2401, 2448, 2449, 2480, 2481MHz.
Fig. 3.9 (a) Measured locking spectrum at 2400MHz
-40dB
Fig. 3.9(b) Measured locking spectrum at 2401MHz
-40dB
-40dB
Fig. 3.9(d) Measured locking spectrum at 2449MHz
Fig. 3.9(e) Measured locking spectrum at 2480MHz
-40dB
-40dB
Fig. 3.9(f) Measured locking spectrum at 2481MHz
Fig. 3.9 shows the output signal power of the frequency synthesizer has approximately 2dB variation from 2.4GHz to 2.481GHz and the reference spur of the frequency synthesizer is -40dB which satisfies the spec of Bluetooth requires.
Fig. 3.10 presents the close loop phase noise of frequency synthesizer which is -102dBC/Hz at 1MHz offset. Fig. 3.11 is the waveform of VCO input control voltage, it represents the locking transient waveforms of the synthesizer. The locking settling time shown is less than 200µs.
-40dB
Fig. 3.10 Measured phase noise of frequency synthesizer
Fig. 3.11 Locking transient of 2480MHz mode VCO Power on
-102dBC/Hz
Locking transient of VCTR
Fig. 3.12 is the frequency hopping transient between 2448 and 2480MHz mode. We adopt function generator to feed a low frequency square wave as mode switching. The hopping settling time is less than 200µs.
Fig. 3.12 Hopping transient between 2448 and 2480MHz
3.4 Summary of Measurement Results
The measured data in this chapter are summarized in Table. 3.1 and 3.2.
Simulation Measurement 2448 mode
2480 mode
Phase noise -108dBc/Hz@1MHz -102dBc/Hz@1MHz
Spurious tones N/A -40dB
Locking time About 80µs About 100µs
Table. 3.1 Summary of specifications
Block Simulation Measurement
VCO 4mA 3.72mA
Buffer 20mA 22mA
Frequency divider 6.4mA 6.7mA
Charge pump 2.8mA 2.7mA
Rest parts of PLL 0.63mA 0.07mA
Total 33.83mA 35.19mA
Table. 3.2 DC current consumption
3.5 Measurement Discussions
The chip manufactured using TSMC 0.25-µm CMOS process suffers from the problem of ESD severely. The gate oxide breaks down easily with inexact operation procedure and without protection circuits. We should give voltage on the gate of PMOS first then increasing voltage on the source side gradually, conversely, give voltage on the source of NMOS first then increasing gate side gradually when turn on the bias circuits. Besides, for decreasing the circuits damaged by pulse, we should add protection circuits at each gate side of biasing circuits as Fig. 3.13 shows.
Fig. 3.13 Protection circuit
The power lines of the testing circuits are also a critical topic to the performance of measurement. Digital or analog power supply is noisy power source, so we add bypass capacitors from 1uF, 1nF, to1pF as near the pad of chip as possible to suppress the noise coming from power source. Besides, adding more via between the top and bottom of the test board and using GSG layout on the power lines and bias lines all can help get more stable bias. Fig.
3.14 shows the testing board with and without the stability equipment.
(a) Testing board before (b) Testing board after modification Fig. 3.14 Measuring board
3.15(b) measures the phase noise which is even -88dBC/Hz, -14dB worse than with pure power source.
Fig. 3.15 (a) Spectrum of frequency synthesizer without bypass capacitor
Fig. 3.15 (b) Phase noise of frequency synthesizer without bypass capacitor
The measuring phase error of quadrature phase is 20° worse than simulation. After analysis, we find the bond wire from the pad to the testing board will induce much phase shift and influence the measuring result. If we assume the chip inside and line of testing board all match to 50 Ω, using Microwave office tool to simulate the length of bond wire with 1µm variation shows that there will be 7° phase difference caused bond wire as Fig. 3.16 shows. Besides, the bond wire causes unbalance LO power in port1 and port4.
The measuring phase error of quadrature phase is 20° worse than simulation. After analysis, we find the bond wire from the pad to the testing board will induce much phase shift and influence the measuring result. If we assume the chip inside and line of testing board all match to 50 Ω, using Microwave office tool to simulate the length of bond wire with 1µm variation shows that there will be 7° phase difference caused bond wire as Fig. 3.16 shows. Besides, the bond wire causes unbalance LO power in port1 and port4.