Measurement Setup

Fig. 5.1 shows the floor plan of the DC-DC buck converter in this thesis. The power transistors are located at the upper side to close the pads so that reduces the resistance on the current path and the voltage drop. The power transistors and the driver are high noise components because a large amount of current flows through them and it could generate high temperature and serious noise disturbance. In order to alleviate the effect upon the feedback circuits, the power transistors must be surrounded by a wide guard ring. The metal which flows through a large amount of current must be wide enough to endure the current density. Every node of power transistors has three pads to reduce the inductance and the resistance of bonding wires. The analog parts are located at the lower side away from the noisy power transistors and separated from the power transistors by digital parts such as the logic gates and the driver.

Fig. 5.1 The floor plan of the DC-DC buck converter

Fig. 5.2 Chip microphotograph

Fig. 5.2 shows the microphotograph of the core chip. The chip is fabricated in 0.35μm 2P4M CMOS technology. The active area is about 1.050 × 0.75mm² and the total chip area including pads is 1.397 × 1.522mm². The layout of the DC-DC buck converter is illustrated in Fig. 5.3. Table 5.1 shows the pin function of the prototype converter.

Table 5.1 The function of the pin in the DC-DC buck converter Pin description

VSS POWER The ground of power transistors

VIN Input voltage

LX Output point of power transistors

VRamp Ramp voltage

Vout Output voltage

VHigh The maximum voltage of Ramp voltage VLow The minimum voltage of Ramp voltage Vref Reference voltage for DAC

SwitchBest Selection of proposed circuit SwitchWorst Selection of conventional circuit

Dv4 The MSB of the input of DAC which controls the output voltage Dv3 The 4^thbit of the input of DAC which controls the output voltage Dv2 The 3^rdbit of the input of DAC which controls the output voltage Dv1 The 2^ndbit of the input of DAC which controls the output voltage Dv0 The LSB of the input of DAC which controls the output voltage Df4 The MSB of the input of DAC which controls frequency

Df3 The 4^th bit of the input of DAC which controls frequency Df2 The 3^rd bit of the input of DAC which controls frequency Df1 The 2^nd bit of the input of DAC which controls frequency Df0 The LSB of the input of DAC which controls frequency ISS1 Bias point of bias circuit which is fast

ISS2 Bias point of bias circuit which is slow

IR EA Bias point of bias circuit which controls the error amplifier

As shown in Fig. 5.4, the measurement environment setup is introduced as following. The LM317 is used to stabilize the power supply and reference voltage of the chip and the Chroma 6300 electronic load is the loading of the DC-DC buck converter.

Chroma 6300 is used at constant current (CC) mode as a stable loading in this work.

The main function focuses on the hopping frequency moment. Firstly, adjust the output voltage by turning on or off the switches of Dv<0:4>. Secondly, choose the expected frequency by turning on or off the corresponding switches of Df<0:4> or feeding in the

digital code by FPGA. Finally, the Oscilloscope Tektronix MSO 4034 is used to measure the voltages and the currents. It is also obtained the transient data and fast Fourier transform (FFT). Some extra passive components are configured according to the requirement shown in Fig. 5.4.

Fig. 5.4 The measurement environment setup

(a) (b)

Fig. 5.5 (a) output stage (b) equivalent circuit of output stage

Due to the second-order response of the output stage affecting the improvement directly, it needs to discuss the component of time constant and damping period [18].

The output stage is organized by an inductor LO, a capacitor CO, and a loading such as a current source IO or a resistor R. Fig. 5.5 shows the equivalent circuit of output stage including the equivalent series resistance (ESR), R and R , of the inductor and

capacitor respectively. The transfer function is given by

The pole frequency ω0 and time constant are obtained from equation (5.1). In this measurement, the ESR of capacitor RC and inductor RL are 20mΩ and 450mΩ respecitively. The ESR of inductor is main different between simulation and measurement. In simulation, it estimates 45 mΩ for ESR of inductor from data sheet and the corresponding time constant is longer. However, the practical ESR of inductor at 2MHz is 450mΩ and the corresponding time constant is shorter in measurement.

Since the ESR of inductor RL is too large to neglect, the improvement of measurement is shrinked than simulation. Fig. 5.6 and Fig. 5.7 are the schematic of the test board. The following Table 5.2 lists the components used in PCB and Fig. 5.8 is the picture of the real test board.

Fig. 5.6 The schematic of power supplies and reference voltages on PCB

Fig. 5.7 The schematic of DC-DC converter side

Table 5.2 The components on PCB for testing the DC-DC converter

Component Designator QTY Description

Uvref, Uvdda, Uvin 3 LM317

Avref, Avhigh, Avlow 3 OP 8031

Lload 1 1 μH inductor

Cload 1 1 μF, 0805 Ceramic Capacitor

Lvref,Lvdda,Lvin 3 Ferrite Bead

JPvref,JPvdda,JPvin 3 Jumper