Feedback-Loop Stabilization

In general, the ripple caused by first term “ESR” is much greater than caused by second term (Ts/8C). So consideration of ESR is essential for estimation of output voltage ripple in switching converter.

2.2.3 Feedback-Loop Stabilization

The simply feedback mechanism is illustrated in Fig. 2.10. The converter is composed of power stage and feedback network. The power stage contains a pair of switching elements, which consists of the power PMOS and NMOS transistors, and an output filter, which consists of an inductor and a capacitor. In feedback network, the difference of βVout which the output voltage is scaled down by resistor series and the reference voltage Vref is fed to the error amplifier. And then the output of the error amplifier and the ramp will pass through the comparator to define the duty cycle (PWM). The duty cycle controls the duration of the conducted time between the PMOS and the NMOS to achieve desired voltage such that the feedback is finished to regulate the output voltage The feedback system can be described as Fig. 2.11. The transfer function of the LC filter is defined as: The transfer function of the feedback network is defined as:

2

where T s3( )HLC( )s H sRR( ).

Fig. 2.10 The simply diagram of the PWM converter

Fig. 2.11 The transfer function of feedback system

It is fixed-amplitude pulse of adjustable turn-on ratio of the PWM modulator. Therefore, the transfer function of the PWM modulator is defined as:

2( ) ^P

T

T s V

V (2.25) where VT is amplitude of ramp waveform and VP is the amplitude of PWM signal. The HRR(s) and T2(s) do not effect on phase shift but they can decay the DC gain. As a result,

there is only error amplifier T1(s) that can provide gain boost to increase the total gain and influence phase for better phase margin.

Next, two types of the error amplifier will be introduced. The first is type II shown in Fig. 2.12 (a), and it has two poles and one zero. The transfer function is calculated as:

2 2 1

The poles locate at the origin and the frequency

2 2

gain in the middle frequency is ²

1

R

R . As a result, appreciate resistors are chosen, and it can compensate the loss caused by the LC filter.

Fig. 2.12 Type II compensator with two poles and a zero

The second is type III, as shown in Fig. 2.13(a), and it has three poles and two zeros.

The transfer function is calculated as:

2 1 1 3 3

The poles locate at the origin, the frequency ₁

In summary, the maximum phase boost in type II compensator is 90 degrees, and in type III compensator is 180 degrees. According to stability and cost, the system will use the appropriate compensator to achieve desired performance.

Fig. 2.13 Type III compensator with three poles and two zeroes 2.3 Variable Frequency

In variable frequency techniques, there are four typical random switching methods discussed firstly. Then we will introduce a simplest method which is frequency hopping (FH). Since the main issue in this thesis focuses on the moment between different frequencies, the FH technique is a good choice to represent the main issue. Therefore, here uses the FH technique in following analysis,

2.3.1 Random Switching

There are four general random switching schemes for switched-mode DC-DC converters, including random-pulse-position-modulation (RPPM), random-pulse-width- modulation (RPWM), and random-carrier-frequency-modulation with fixed-duty-cycle (RCFMFD) and with variable-duty-cycle (RCFMVD), respectively. They are categorized by the random modulation of pulse which drives power transistors. The parameters of pulse are shown in Fig. 2.14. Tk is the duration of the kth cycle. εk is the delay time of the pulse. αk is the duration of the pulse in the kth cycle. dk which equals to αk/Tk is the duty cycle period of the switch turning on in the kth period. The amplitude of pulse is rail to rail of input voltage. Their operation will be addressed as following paragraphs.

Fig. 2.14 Switching parameters

RPPM is similar to the classical PWM scheme with constant switching frequency.

However, the position of the gate pulse or delay time εk is randomized within each switching period, instead of commencing at the start of each cycle. RPWM allows the pulse width αk to vary, but the average pulse width is equal to the required duty cycle.

RCFMFD exhibits randomized switching period Tk and constant duty cycle d=αk/Tk, while RCFMVD exhibits randomized switching period Tk and constant pulse width α.

With the aid of Fig. 2.15, the characteristics of the pulse g(t) in each scheme are summarized in Table 2.1.

Fig. 2.15 Switching signal with randomized modulation (a)RPPM (b)RPWM (c)RCFMFD (d)RCFMVD (e)FH

Table 2.1 Characteristics of different random switching schemes Switching

schemes

Tk αk d=αk/Tk εk

Standard PWM

Fixed Fixed Fixed Fixed RPPM Fixed Fixed Fixed Randomized RPWM Fixed Randomized Randomized Fixed RCFMFD Randomized Randomized Fixed Fixed RCFMVD Randomized Fixed Randomized Fixed

FH Integer sets Integer sets Fixed Fixed

2.3.2 Frequency Hopping

Compared to random switching schemes, the frequency-hopping (FH) technique utilizes couples of fixed switching frequencies to achieve EMI-peak reduction. Using predictable frequencies relax the complexity of the filter. Its characteristic of the pulse is shown in Fig. 2.15(e). The spectrum results of these variable frequency techniques are shown in Fig. 2.16. Table 2.2 aids to understand each reduction for peak of EMI.

Another issue is the output voltage in time domain. In Fig. 2.17, these techniques have different phenomena in steady state. The reason is that the duty cycle varies in RPWM and RCFMVD.

(a) (b)

(b) (d)

(e) (f) Fig. 2.16 Output spectrum of different switching schemes

Table 2.2 Comparison of different switching schemes Switching

schemes

Peak of EMI (dB) Standard

PWM

50.77 RPPM 50.61

RPWM 50.4

RCFMFD 49.56 RCFMVD 48.56

FH 44.48

Fig. 2.17 Transient waveform of different switching schemes

Chapter 3 Proposed Architecture

3.1 Introduction

The inductor current average control (ICAC) is proposed in this paper. When using variable frequency techniques such as random switching or frequency hopping (FH), the inductor current ripple varies as the switching frequency changes. This variation of current ripple results in a transient ripple on the output voltage and undesired spur. In order to reduce this effect, this thesis discusses the best moment between different frequencies and how to implement. As aforementioned, the main issue focuses on the best moment between different frequencies and the FH technique adapts to this situation.

Therefore, it discusses the hopping moment in following analysis 3.2 Specification of DC-DC Buck Converter

The preliminary specification of DC-DC buck converter of this design is shown in Table 3.1. This work is used in portable devices to drive power amplifiers of RF circuits such as power-level tracking [14]. Therefore, the off-chip components must be small (LO>4.7μH and CO>10μF in conventional circuits) and the output current is determined by the power amplifier. Output voltage range is utilized to the standby mode and active mode in portable devices for saving power. Input voltage range is determined by the battery type. Switching frequency is usually fixed in typical PWM converters, but in spread spectrum methods such as frequency hopping (FH), it needs a particular frequency range.

Table 3.1 Specification of designed DC-DC buck converter.

Specification Parameters

Input voltage, VIN 3.6-5 V

Output voltage, vOUT 0.8-3.4 V Max. output current, IO 450 mA Output inductor, LO 1 μH Output capacitor, CO 1 μF Switching frequency, freq 2-3 MHz

3.3 System Architecture

In this chapter, the detailed operation of the chip will be discussed. The typical architecture is illustrated in Fig. 3.1. A PWM buck converter provides a regulated output voltage vOUT from an unregulated input voltage VIN. The PWM controller compares the ramp signal, vramp, with the output of the error amplifier to generate a square wave, vPWM, for voltage regulation. The gate driver drives the power transistors, MP and MN, with dead-time control to avoid a shoot-through current. The power transistors induce current passing a low pass filter which is composed with an inductor, LO, and a capacitor, CO to the load, IO. Note that the frequency of vramp determines the operation frequency and is able to change for hopping the frequency.

Fig. 3.1 Structure of a conventional PWM buck converter.

3.4 Inductor Current Average Control (ICAC)

As shown in Fig. 3.2, the FH technique with a lower frequency, f1, and a higher frequency, f2 [5] can avoid the energy concentrated on a single frequency at fnohop. Their magnitudes are 6dB down as two frequencies hopping in comparison with the magnitude at only one frequency. However, the converter output suffers transient ripples for several periods after hopping and it would result in an undesired spur at ftrans.

Fig. 3.2 Energy spread to multiple frequencies with the FH technique.

As shown in Fig. 3.3, in conventional PWM DC-DC converters [3], it assumes the frequency hopping at falling edge of vPWM for simplicity and random in practically. The inductor current, iL, increases during on duty cycle period, and decreases during off duty cycle period. In the example of Fig. 3.3, Ton,1 and Ton,2 represent the on duty cycle period of switching period at the low and high frequencies respectively. Toff,1 and Toff,2 represent the off duty cycle period of switching period at the low and high frequencies respectively. It reaches its peak/valley currents at the rising edge or the falling edge of vPWM. After the hopping moment, the average of the transient inductor current would be different from that of the steady-state inductor current, IL, due to the current continuity property of inductor. But, it would gradually approach IL when the inductor current is back to steady state. Therefore, the difference, ΔIL,trans, charges (or discharges) CO and generates transient ripple, Δvtrans on the output voltage. Its frequency response is the undesired spur at ftrans is dominated by LO and CO [15]. The undesired spur can be reduced by a larger capacitor but it pays a longer time to settle. Or, a larger inductor can be used but it occupies a larger area in the circuit.

An Inductor Current Average Control (ICAC) technique for FH structure is

proposed in this paper. As shown in Fig. 3.4, the best hopping moment could be chosen.

The best time length, TX, is calculated to correspond to the best hopping state, which maintains the same IL between the two frequencies. It modulates the off/on duty cycle period to be TX width. The calculated value of TX will be discussed in detail later. In the proposed hopping state, the output ripple voltage is improved by making the amount of charging close to the amount of discharging in the capacitor. If transient ripple on the output voltage is reduced, the undesired spur at ftrans in Fig. 3.4 is also reduced.

The best hopping state can be derived either in the off duty cycle period or the on duty cycle period. The proposed technique for FH from low to high and from high to low in these two different duty cycle periods will be discussed separately. Note that hopping in the off duty cycle period using ICAC is implemented in this chip.

Fig. 3.3 Transient waveforms of output voltage, inductor current and PWM signal in a conventional converter.

Fig. 3.4 Transient waveforms of output voltage, inductor current and PWM signal in the converter with the proposed ICAC technique.

3.4.1 Hopping in Off Duty Cycle Period

As mentioned before, there are two choices to hop, here discusses hopping in off duty cycle period with two parts. One is the frequency hopping from low to high, and another is the frequency hopping from high to low.

3.4.1.1 Hopping frequency from low to high

To reduce the complexity of transient response analysis, the loading is supposed to be a constant current source, IO as indicated in Fig. 3.1. Therefore, the load current IO is equal to the average or dc current IL.

Q2

Q_hop

T₂ T₂ T_on,1 T_off,1

Q1

(a)

(b)

Fig. 3.5 (a) Conventional and (b) proposed transient inductor current that hops frequency from low to high in off duty cycle period.

As shown in Fig. 3.5(a), the net charge on the capacitor, ΔQ, after t0 is

1 2

Q Q

hop

Q Q

    

(3.1)



I_Xhop-I_O



t_hop-t0

 ^

I_X1-I T_O

^{ }

2 I_X2-I T_O

^

2

   

where IXhop is the average of transient inductor current from t0 to thop and IXi, i=1,2,… is the average of transient inductor current at the ith period of vPWM after t0. t0 is the time at which the inductor current is at its peak or valley and the capacitor voltage is at its dc value, VO. thop is the hopping moment. T2=Toff,2+Ton,2 is the period of vPWM after hopping.

The transient response can be separated into two parts, the charge in the hopping interval Qhop and total charge after hopping QT=Q1+Q2+…. Since settling time is longer than one period, Qhop is much smaller than QT.

hop T T

Q Q Q Q

   (3.2) As illustrated in Fig. 3.5(a), QT is approximated with a triangular area. Its height is the difference between IO and IX1. Its width, TT, is the time from thop to the steady state. where ilp-p,1 and ilp-p,2 are the peak-to-peak values of the inductor current at low frequency and high frequency respectively. moff is the slope of the decreasing inductor current. D is the duty cycle.

Then, the conventional transient ripple on the output voltage can be obtained as

1 2

where T1, T2 are the periods of the low and high frequencies respectively.

In order to minimize QT in (3.3), the best time TX of thop is proposed as follows. In

the proposed best time TX can be calculated as period at low and high frequencies. Its corresponding transient waveform is illustrated in Fig. 3.5(b). Since IX equals IO, according to (3.3), only the rest of charge, Q1, would affect transient ripple of the output voltage.

- ,1 ,1 - ,2 ,2

According to (3.5) and (3.10), the conventional and proposed transient ripples on the output voltage are proportional to (T1-T2)TT.and (T1-T2)TX respectively.

3.4.1.2 Hopping frequency from high to low

As shown in Fig. 3.6(a), when the frequency hops from high to low, the average of transient inductor current IX1 is over the average inductor current IO. Similarly, IX1 can be approximated as when it hops from high to low. It is the average of off duty cycle period at low and high

frequencies.

(a)

(b)

Fig. 3.6 (a) Conventional and (b) proposed transient inductor current that hops frequency from high to low in off duty cycle period

3.4.2 Hopping in On Duty Cycle Period

3.4.2.1 Hopping frequency from low to high & from high to low

Similar to the analysis in 3.4.1, the only different part is the average of transient

   

1 - ,1 0 - ,2

1 1

2 - 2

X hop O lp p on hop lp p

I t I  i m  t t  i (3.12)

   

1 - ,2 0 - ,1

1 1

2 - 2

X hop O lp p on hop lp p

I t I  i m  t t  i (3.13) IX1 in (3.12) is hopping from low to high and IX1 in (3.13) is hopping from high to low.

Let IX1 in (3.12) and (3.13) equals to IO as shown in Fig. 3.7 and Fig. 3.8 respectively, we obtain the similar TX=t-t0=¹₂(Ton,1+Ton,2). It is the average of on duty cycle period at low and high frequencies

Fig. 3.7 Proposed transient inductor current that hops frequency from low to high in on duty cycle period.

Fig. 3.8 Proposed transient inductor current that hops frequency from high to low in on duty cycle period.

Chapter 4 Circuit Implementation and Simulation Results

Based on above analysis, the proposed system circuit is shown as Fig. 4.1. Except for the conventional buck converter architecture, there are two DACs and an ICAC block. Two DACs change the output voltage and the switching frequency respectively.

An ICAC block before the gate driver block is utilized to insert a calculated-width pulse for modulating the best time in frequency hopping.

Rf1

4.1 Amplifier Circuit

There are two type amplifiers in this work. One is slower and only used in the error amplifier circuit. Another one is faster and provides higher DC gain in this work which needs operational amplifiers (OP).

4.1.1 Error Amplifier

There are many compensation methods such as type II and type III. But as the operation frequency changes in the FH technique, the feedback-loop stabilization is much more difficult since these methods compensate the particular frequency range.

Based on the simplicity and independence from the switching frequency, a dominant-pole compensation is used in this error amplifier to compensate the stability of the system.

To avoid any second pole involving in this dominant pole, it uses a one-stage simple operational amplifier as shown in Fig. 4.2. The unit-gain frequency ωt is given by

t ^m1,2 C

g

  C (4.1) There are two components which define the unit-gain frequency. Firstly, to make lower unit-gain frequency for dominant-pole compensation, the compensation capacitor CC is chosen as large as possible and is limited by the area on chip. Secondly, another component is the transconductance of input transistors, gm1,2.

m 2 OX D

g C W I

 L (4.2) To make smaller gm, it is chose p-input, small W/L ratio and small bias current Itail=2ID.

in

=V_{ref_ea}

v_A V_{bias_ea}

M0

M1 M2

M3 M4 C_C

Itail

in

=βv_OUT

Fig. 4.2 Schematic of the error amplifier

Fig. 4.3 shows the AC analysis of the error amplifier. Open loop DC gain is 44 dB.

Phase margin is 90 degree and the unity gain bandwidth is 113 kHz as CC=42 pF.

Gain (dB)

Phase (degree)

4.1.2 Operational Amplifier

In order to provide high DC gain, it chooses the folded-cascode structure as shown in Fig. 4.4 [11]. Its DC gain AV and 3dB frequency ω3dB are given by It is necessary to add an output stage when it drives resistance load. Therefore, some of these OPs have a NMOS common-drain stage as output buffer as listed in Table 4.1. Table 4.1 also shows two different tail currents. Several operational amplifiers do not need high frequency response, so they could use smaller tail current to save power.

As shown in Fig. 4.5 and Fig. 4.6, their DC gain and 3dB frequencies are 69 dB, 43 MHz and 61.5 dB, 16 MHz respectively. The DC gain of OP with output buffer is lower due to the body effect. From Fig. 4.7, we have

1 2

Equation (4.5) represents that body effect decreases the DC gain. Although it can by reduced by using PMOS common-drain stage, it needs a shift-down circuit rather than shift-up circuit in this work.

Fig. 4.4 Schematic of folded-cascade operational amplifier Table 4.1 OP types used in this work

Itail=2 μA Itail=5 μA With Buffer

Subtractor O O

Input of RampGen. O

Input of S&H O O

Buffer of Vref O

Buffer of vA O O

Buffer of vramp O O

Fig. 4.5 Frequency response of the OP-Amp without output buffer

Fig. 4.6 Frequency response of the OP-Amp with output buffer

(a) (b)

Fig. 4.7 Common-drain output buffer (a) circuit. (b) small-signal equivalent circuit

4.2 Comparator Circuit

A comparator is a circuit that compares the instantaneous value of an analog input voltage with a reference voltage, and then generates a logic output level depending on whether the input is larger or smaller than the reference level.

As shown in Fig. 4.8, it is implemented by a source-coupled differential pair with positive feedback to provide a high gain. The gain of the positive feedback gain stage is given by

where α=(W/L)5/(W/L)3 is the positive feedback factor.

The inverter chains are used to increase the response of the output signal and pull the output to digital level. The inverter stage acts as a driver stage such that the size of M7 and M8 can be made smaller. With the smaller size of M7 and M8, the effect of the parasitic capacitance at the gates of M7 and M8 is decreased for a faster response.

Fig. 4.8 Schematic of the comparator

The comparators are needed one for the PWM controller, two for the ramp generator circuit (RampGen.0), two for the detector and two for the calculated pulse circuit (RampGen.1 and RampGen.2) in the ICAC block.

4.3 Ramp Generator Circuit

The ramp generator is the circuit which generates a ramp signal for PWM controller as shown in Fig. 4.9. To clamp the upper band VHigh and lower band VLow, there are two comparators and one SR latch in the right side of Fig. 4.9. The reference voltage Vref_ramp provides a current it through a resistor Rt and it is given by

The ramp generator is the circuit which generates a ramp signal for PWM controller as shown in Fig. 4.9. To clamp the upper band VHigh and lower band VLow, there are two comparators and one SR latch in the right side of Fig. 4.9. The reference voltage Vref_ramp provides a current it through a resistor Rt and it is given by

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