1 10 100 1000 10000
-140
Fig. 5.11 Measured and simulated phase noises of the proposed VCO.
frequency with the center frequency at 5.14 GHz and an output power of -2.4 dBm. In addition, the FOM has been used and defined as follows to compare the performances of VCOs [70]:
{
offset}
c DCoffset
FOM 20 log 10 log ,
1mW
f P
L f f
⎛ ⎞ ⎛ ⎞
= − ⎜⎝ ⎟⎠+ ⎜⎝ ⎟⎠ (5.2)
where L{foffset} is the measured phase noise at an offset frequency foffset from fc carrier frequency, and PDC is the total VCO power dissipation in mW. Following this definition, the measured FOM of the proposed VCO is -190 dBc/Hz at the offset frequency of 1 MHz.
5.4 SUMMARY
A low-power VCO with phase noise improvement has been designed and fabricated using 0.18-μm CMOS technology. Based on the current-reused configuration, a larger value of capacitor C1, an additional capacitor CT, and the appropriate bulk bias voltage Vb of the transistor are adopted to achieve a better phase noise performance. The measured results of the proposed VCO agree quite well with the simulated results. The performances of the VCO are listed in Table 5.1 and compared with those of others.
Table 5.1
Performance summary of the low phase-noise VCOs
Ref. Tech. Freq.
[GHz]
PN @1Mz [dBc/Hz]
Pdiss
[mW]
Area [mm2]
FOM [dBc/Hz]
[70] 0.13 μm
CMOS 5.98 -115 12.5 - -180
[71] 0.18 μm
CMOS 4.5 -122.5 6.75 0.55 -187
[72] 0.18 μm
CMOS 5.1 -116.7 3.9 0.5 -185
[73] 0.18 μm
CMOS 5.6 -110.8 8.3 0.5 -177
[74] 0.18 μm
CMOS 5.2 -113.7 9.7 0.35 -180
This work
0.18 μm
CMOS 5.25 -119 1.9 0.15 -190
CHAPTER 6 CONCLUSIONS
In this thesis, the design methodologies and implementations of key CMOS RFICs including two triple-band LNAs, a dual-band image rejection mixer, three low-power UWB LNAs, and a VCO for multiband and UWB communication systems are proposed.
Firstly, the design of two triple-band LNAs with switched resonators is presented and fabricated in a TSMC 0.18-μm CMOS process. The proposed triple-band LNAs are demonstrated the feasibility to effectively decrease the size of multi-band RF systems by using a switched component. In addition, the feedback noise-canceling technique and the noise reduction resistor RB will effectively diminish the output noise power density. It can be observed that 1.5/1.3/1.1 dB noise figure decrease can be attained at 2.5/3.5/5.2 GHz in the second LNA without extra dc power and CMOS process steps.
Secondly, a 2.45/5.2 GHz image rejection mixer with differential dual-band third-order notch filter has been fabricated and designed. The proposed differential dual-band image rejection circuitry is employed for the 2.45/5.2 GHz WLAN application to effectively diminish the dc power consumption and complexity of circuit design compared to the traditional Hartley or Weaver architectures. Moreover, the cross-connected pair consisted of NMOS and PMOS transistors in the proposed notch filter will further ameliorate the image rejection capability. The suppression of about 36/45 dB at the image frequencies can be achieved without worsening the in-band characteristics.
Thirdly, three low-power UWB LNAs using 0.18-μm CMOS technology are
presented. Extra transmission zeros are created in the first UWB LNA due to the use of a LC input network with additional capacitors CRH and CRL for improving the higher and lower out-band performances respectively. Moreover, a feedback structure and dual-band notch filter with low power active inductors will further attenuate the outband interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5 dB minimum noise figure can be measured while consuming a dc power of only 5 mW. Finally, a new matching technique by selecting an appropriate width of the transistor M2 is presented to further ameliorate the noise figure performance in the third UWB LNA. The IC prototype achieves good performances such as a power gain of 16.2 dB, a better than 10 dB input return loss, and 2.3 dB minimum noise figure while consuming a dc power of only 6.8 mW.
Finally, a low-power 5.25 GHz VCO with phase-noise improvement is designed in a 0.18-μm CMOS 1P6M process. Based on the current-reused configuration, a larger value of capacitor C1, an additional capacitor CT, and the appropriate bulk bias voltage Vb of the transistor are adopted to achieve a better phase noise performance. A good FOM of -190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a power consumption of 1.9 mW and active chip area of 0.15 mm2. The measured phase noise at 1 MHz offset is about -119 dBc/Hz.
APPENDIX
Abbreviation Full name
ADS Agilent Advanced Design System
CMOS Complementary Metal Oxide Semiconductor FCC Federal Communications Commission
FOM Figure of Merit
GSM Global System for Mobile
ICP Inductively Coupled Plasma
IP1dB Input-referred 1-dB Compression Point IIP3 Third-order Input Intercept Point ISF Impulse Sensitivity Function
LNA Low-Noise Amplifier
MB-OFDM Multi-Band Orthogonal Frequency Division Multiplexing
MIMO Multiple-Input, Multiple-Output
OFDM Orthogonal Frequency-Division Multiplexing RSSI Received Signal Strength Indicator
RFICs Radio Frequency Integrated Circuits
SSB Single Sideband
TSMC Taiwan Semiconductor Manufacturing Company UWB Ultra-WideBand
VCO Voltage-Controlled Oscillator
WiMAX Worldwide Interoperability for Microwave Access
WiFi Wireless Fidelity
WLAN Wireless Local Area Network
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