5.1 INTRODUCTION
The VCO is an important unit among the building blocks of a RFtransceiver.
Thedesign considerations of a VCO include operation frequency band, phase noise, power consumption, and tuning range. Among the various architectures of the VCO, the cross-coupled oscillator is attractive for its design simplicity and start-up oscillation condition. The proposed VCO is thus based on this structure to ameliorate the noise performance.
Phase noise is one of the most critical parameters since it affects the overall performance of a communication system; therefore, there are numerous attempts in the design of VCO to optimize the phase-noise performance. The harmonic tuned LC tank inFig.5.1is employedto attenuate the second harmonicpower while maintaining a superior fundamental power, which is benefic to make the output voltage waveform steeper for reducing flicker noise of transistor [67]. The phase-noise suppression is achieved bymaximizing theslope ofthe output voltage at the zero crossing point.
However, it is inevitable to result in a high implementation cost because the additional on-chip inductors are required. On the other hand, the ICP deep-trench technique in Fig.5.2, which selectively removes the silicon underneath the inductors, also can be utilized to improve the phase noiseof a VCO[68]. Nevertheless, theextra CMOS process steps will raise the complication of circuit implementation.
Fig. 5.1 The phase-noise suppression with the second harmonic tuned LC tank [67].
Fig. 5.2 Process steps of the backside ICP deep trench etching technique [68].
In this chapter, we adopt the design of a current-reused configurationbecauseof itsexcellentlow-powercharacteristic and focus on the improvement of phase-noise performances without additional chip area and CMOS process steps. By a larger parallelcapacitor,anextra harmonic-rejected capacitor, and an appropriate bulk bias voltage of transistor, a good figure of merit (FOM) of -190 dBc/Hz will be attained.
Fig. 5.3 Complete schematics of the proposed low-power VCO with the phase-noise reduction techniques.
5.2 CIRCUIT DESIGN
The proposed VCO, as shown in Fig. 5.3, uses the cross-connected pair consisted of NMOS and PMOS transistors as a negative conductance generator. Power consumption and the usage of inductors can be cut in half compared to the traditional VCO while providing the same negative conductance. Furthermore, a center-tapped spiral inductor L1 is employed to obtain a symmetricaldifferential output signals at nodes V＋ and V－. When the voltage at node V＋ is high, the proposed VCO is equivalent to that shown in Fig. 5.4 (a), where the transistors M1p and M1n operate in the triode region. The impedance observed from the inductor L can be regarded as the
Fig. 5.4 The equivalent circuits of the proposed VCO when the voltage at node V＋ is (a) high and (b) low.
capacitorC1’ inparallel with the triodemode resistors (i.e., a smaller impedanceis acquired). On the other hand, when the voltage at node V＋ is low, the circuit is equivalent to that in Fig. 5.4 (b), and the impedance observed from the inductor L1
becomesonly that ofthe capacitorC1’.An obvious impedance difference will arise when V＋ changes in between high and low statuses, which means that an unbalanced voltage swing at node V＋ will be generated. This in turn will deteriorate the phase-noise performance. In order to improve this drawback, a larger value of the capacitor C1’ (i.e., a smaller impedance) is required to maintain the similar impedances in both operation statuses. It can be observed from Fig. 5.5 that a larger capacitor C1’ effectively provides a balanced voltage swing at node V＋ to ameliorate phase-noise characteristic.
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The suppression of the second harmonic power with the series L-C sections has been utilized to improve the phase noise of a VCO [67]; however, the extra inductors will occupy additional chip area, which makes it undesired for low-cost application.
In this study, we introduce an additional capacitor CT in the VCO circuit (Fig. 5.3) to attenuate the second harmonic signal, as shown in Fig. 5.6. To begin with, it can be anticipated that node A is a virtual ground due to the differential outputs of the fundamental signal, and this means that the existence of the capacitor CT will have no influence on the oscillation frequency. However, the in-phase second harmonic signals can be suppressed by the usage of a suitable capacitor CT because a series resonance is produced. Fig. 5.7 shows the measured results of the output signal with and without the additional capacitor CT, and it can be observed and demonstrated that a 12 dB decrease in the second harmonic power is attained. Consequently, the introduction of the capacitor CT can effectively diminish the second harmonic signal
Fig. 5.6 Influence of the capacitor CT for (a) the fundamental signal and (b) the second harmonic signal.
Fig. 5.7 Measured output signals with and without the capacitor CT .
On the other hand, the 1/f3 corner in phase noise spectrum can be given from [69] second Fourier series coefficients of the impulse sensitivity function(ISF). From(5.1), the 1/f3 corner of the phase noise spectrum can be reduced by selecting a larger channel width W; however, this will indirectly increase the value of the transconductance gm, which is proportional to the size of transistor. To overcome this drawback, here we introduce the additional bulk bias voltages Vbp and Vbn of the transistors, as shown in Fig. 5.3, for further obtaining a smaller gm. By providing an appropriate bulk bias voltage, the threshold voltage can effectively be raised to diminish the current of transistor since the threshold voltage is governed with the body effect.
Fig. 5.8 shows the simulated results of phase noise characteristics with and without improvement. It can be observed and demonstrated that a 15 dB decrease at 10 kHz offset frequency can be attained due to the usage of a larger capacitor C1, an extra capacitor CT, and the appropriate bulk bias voltage Vb.
5.3 EXPERIMENTAL RESULTS
The microphotograph of the low-power VCO fabricated by 0.18-μm TSMC CMOS process is shown in Fig. 5.9. The core chip area is 0.33×0.45 mm2, and the core dc power dissipation is 1.9 mW. The value of Ro in the proposed VCO is set as