Chapter 1 Introduction
1.3 Mismatch in Subthreshold Region
1.3 Mismatch in Subthreshold Region
It is well known that there are no two things identical in the world. This is the case for MOSFETs. Even in the same size, there are no two transistors that are identical because of the variation of manufacturing process. Pelgrom [4] pointed out that the mismatch of MOSFET is proportional to the inverse square root of gate area and are proved experimentally. Therefore, as the dimension of semiconductor device continues to be reduced with today’s technology, mismatch becomes more and more important. From the research works of [5] ,we can clearly know that back-gate bias has a very huge relation with current mismatch and the back-gate forward bias can suppress it. Thus we should simultaneously take both device area and back-gate bias into account during the mismatch analysis.
As we mentioned above, one of the advantages of subthreshold region is the exponential dependence of drain current on gate voltage. But on the contrary, this relation is also to cause the large mismatch especially in the small device. Different from the dependencies following the square rule for operating in above-threshold region, the subthreshold region of operation has the exponential dependencies on process parameters. Therefore, it is expected that drain current exists larger mismatch in subthreshold region than that in the above-threshold region as shown in Fig 1.
In subthreshold region, there are many parameters to form a mismatch model,
while our parameters will be based on threshold voltage, drain-induced barrier lowering and subthreshold swing are included. In order to reduce the mismatch effectively, we can operate the device with back-gate forward bias applied. So, with the device area decreasing, the mismatch increasing can be compensated by the back-gate forward bias. This characteristic will make the subthreshold operation become more attractive.
Chapter 2
Parameters of Mismatch
2.1 Experimental Subthreshold Operation
The measurement of mismatch for identical devices was achieved in terms of the dies in wafer. In this thesis, we used the measured capacitance-voltage(C-V) curve fitting by Schred simulator to obtain the parameters due to the manufacturing processes. They are: gate oxide thickness is 1.27nm , n+ doping concentration is
20 3
1 10 cm and the substrate doping concentration is 4 10 cm 17 3. All dies on wafer contain many n-channel MOS transistors with the same structure. All of them were fabricated using a 65nm CMOS process. The devices under study were n-channel MOSFETs with varying gate widths ( W =0.13 m , 0.24 m , 0.6 m , 1 m , 10 m ) and mask gate lengths ( L =0.065 m , 0.1 m , 0.5 m , 1 m ).
In our measurement, the p-well-to-n+-source bias V was fixed with the gate BS voltage sweeping from 0 V to 1.2 V in a step of 25 mV. The drain current was measured and recorded for subsequent analysis. All the procedure was performed under four different back-gate bias: -0.8 V, -0.4 V, 0 V, and 0.4 V, the same as which applied in [5]. In order to make sure of the action of the gate lateral bipolar transistors, the choice for maximum forward bias is equal to 0.4 V. The drain voltages that we chose are two values, one is fixed at 0.01 V in the subthreshold region, and the other value is 1 V for extracting the drain-induced barrier lowering.
The measurement setup contains the HP4156B and a Faraday box which is used for shielding the test wafer. All were performed in an air-conditioned room with the temperature at 298 K. We operate the n-channel MOSFET devices in the weak
inversion region. Fig. 2 displays typical measured I-V characteristics with back-gate bias parameter on a single n-channel MOSFET.
2.2 Extraction of Threshold Voltage
characteristics. While the latter method is quite common to be used, there are various methods to extract threshold voltage [6] and they have been given several distinct definitions.In order to extract the threshold voltage in subthreshold region, we choose the constant current method to extract the threshold voltage in this thesis. The constant method evaluates the threshold voltage as the value of the gate voltage, corresponding to a given constant drain current measured at drain voltage less than 100mV. A typical
value [7] for this constant drain current is m 10 ( )7 the mask channel width and channel length. The threshold voltage can be determined with voltage measurement as shown in Fig. 3. From Fig. 3, we can observe there are large sample number (2000) used in measurement. All threshold voltages we extracted for this chosen current are from the subthreshold region. The threshold voltage values of all device sizes we obtained by constant current method are shown in Fig. 4.
2.3 General Mismatch Model
The mismatch parameters of a group of equally designed devices are the result of several random processes encountered during the fabrication phase of the devices.
According to [3], the standard deviation f x y( , ) of a function f x y
,
with two parameters while using this model. If there is no correlation between each other, we can get the simplest formula for the mismatch model. So, we need to confirm the parameters are independent every time we want to build a new mismatch model. But we all know that everything in the world may affect each other. In the following chapters, we will use Eq. (1) as the threshold voltage fluctuation model, and the correlation coefficient may be negligible due to the weak relation between different parameters in our mismatch model.2.4 Subthreshold Swing
In order to evaluate the value subthreshold leakage current, subthreshold swing is defined as the gate voltage variation per decade of current. It is found from [8]:
( )
log 2.3 the thermal voltage kT 0.0259
q V at room temperature. The ideal value of subthreshold swing is 60mV decade for n is equal to / 1 . The results of subthreshold swing extracted from experimental data are shown in Fig. 5. The extracted subthreshold swing will be used in following chapter.
2.5 DIBL Effect on Threshold Voltage
As the advance in technology, channel length is scaling down. It is gradually important to consider short-channel effect and drain-induced barrier lowering (DIBL).
Here we focus on the DIBL effect. In order to further discuss the DIBL, we derive a mismatch model of DIBL as a parameter of threshold voltage fluctuation. In this work, we use constant current method to determine the threshold voltage for large drain voltage.
DIBL is defined as the threshold-voltage shift divided by the drain voltage change. It can be expressed as:
1 1 0 0
For using the DIBL we extracted to examine the mismatch model, we write Eq. (4) as another form:
1 ( 0 1)
th d d th
V V V DIBL V (5)
According to Eq. (1) and Eq. (5) and assume the correlation is negligible, we can derive the mismatch model:
1
2 2 2 2
0 1
Vth Vd Vd DIBL Vth
(6) where Vd0Vd1 0.99V in our case. Similarly with the threshold voltage standard deviation, the DIBL standard deviation also has inverse relation of the device size as shown in Fig. 8. Fig. 9 demonstrates the experimental data and the calculated results of the model, where we can observe that the results are as anticipating as we can infer.
Thus we can write the standard deviation of DIBL as a function of threshold voltage for different drain voltages.
Chapter 3
Random Threshold Voltage Fluctuation
3.1 Channel Doping Concentration
Along with the advanced technology, device size is more and more small.
Channel doping concentration becomes an essential parameter of MOSFET. From threshold voltage we display before, we observed when the channel length gets shorter, the threshold voltage might become larger. Contrary to the short channel effect, it is widely known that heavy channel doping may increase the threshold voltage. Consequently, we consider that the halo doping (near the source/drain and under the inversion channel) will affect the effective channel doping concentration
_ A eff
N to bring about this phenomenon. The schematic drawing of halo doping device is shown in Fig. 10.
In order to find the effective channel doping concentration of our experimental data, we start at finding the flat band voltage VFB. The flat band voltage is defined as the gate voltage at zero band bending. From semiconductor physics studied, we understand that the existence of many kinds of traps may affect the flat band voltage, such as oxide trap, interface trap and fixed oxide charge. It is difficult for us to quantify each of them. Because of this, we attempted to use the threshold voltage we have extracted from constant current method to obtain the flat band voltage including the trap effect.
First, the formula of threshold voltage can be derived as:
2 2
th FB f f BS
V V V (7)
ln A long channel effect by halo doping can be negligible. Thus we can use the extracted threshold voltage from five different gate widths (W =0.13 m , 0.24 m , 0.6 m , 1 m , 10 m ) at longest gate length ( L =1 m ) and N =A 4 10 cm 17 3and according to Eq. (7) to obtain five different flat band voltages with corresponding gate widths.
The extraction result is shown in Fig. 11.
Next, with the flat band voltage we have extracted and the threshold voltage of other gate lengths ( L =0.065 m , 0.1 m , 0.5 m ), similarly, according to Eq. (7), we can obtain the effective channel doping concentration NA eff_ of different gate
lengths as shown in Fig. 12. In order to confirm if NA eff_ we extracted is reasonable, we substituted them into the Eq. (7) for different back-gate bias to derive the corresponding threshold voltage, and then compared the results with the experimental data. As a result, we find that they almost match the experimental data as shown in Fig. 13.
Although these effective channel doping concentrations we extracted may be not the real doping concentration of the MOSFETs, but it can reveal the characteristics of channel doping concentration. Thus we can use them for the undertaken study as an
equivalent channel doping concentration of our devices.
3.2 Random Threshold Voltage Fluctuation
One of the important things of operating the MOSFETs is the applied voltage.
The applied voltage is being steadily lowered to reduce the power consumption and keep the reliability. There are many factors that may affect threshold voltage fluctuation, such as random dopant, oxide thickness, oxide interface roughness and polysilicon gate enhancement [9]-[13]. In this chapter, first, we start at models from Takeuchi’s paper [14],[15], and repeat some work of threshold voltage fluctuation.
Next, we use a model of random dopant threshold voltage fluctuation, to evaluate the threshold voltage fluctuation induced by random dopants. Finally, we eliminate the random doping effect of threshold voltage fluctuation to find others effect of threshold voltage fluctuation and give a discussion.
The vertical electric field in this model is a function of depth x in the channel region. If there is an extra charge sheet Q added within the channel depletion layer, we assume the voltage drop between the surface and the depletion region edge (xWDEP) is constant. Thus the relationship between threshold voltage charge sheet can be shown as a function of charge sheet Q and depth x : volume is of binomial type, thus the standard deviation of Q will be:
SUB( ) length. Therefore, the standard deviation of the threshold voltage can be obtained by
integrating the contributions of the charge sheets from x0 to xWDEP Eq. (12) can be slightly modified into:
3
Threshold voltage formula is written as follows:
2 SUB DEP
Substituting the Eq. (15) to Eq. (14), we can derive:
( 2 ) mentioned above. As the flat band voltage and effective channel doping concentration we have mentioned above, our results of this part is shown in Fig. 14. Since the fluctuation model has offered an effective way to compare and analyze the different kinds of transistors manufactured by different processes. The substrate bias dependence of threshold voltage standard deviation also can be properly normalized base on this fluctuation model. From Fig. 14, we can observe that the effect of the back-gate bias according to the fluctuation model has the same trend in agreement with our experimental data.
Next, we discuss the well known fact that the V standard deviation commonly th
satisfied the relationship:
oxide thickness and threshold voltage, the results of this model are shown in Fig. 15.
From Fig. 15, we can observe obviously that the V standard deviation is being th proportional to the inverse square root of the device area, and the mismatch became severe with back-gate reverse bias. The result agrees well with the arguments as mentioned above.
3.3 Random Dopant Induced Threshold Voltage Fluctuation
In above statements, we assume that impurity in the channel region has most tremendous influence on threshold voltage fluctuation. As MOSFET scales down to the deep submicrometer feature size, the intrinsic spreading in various parameters also is a significant factor in the matching performance of the identically transistors. In fact, the random dopant also plays an important role in the threshold voltage fluctuation model.
In this work, we consider the effect of random dopant on the threshold voltage fluctuation of the MOSFETs. The depletion region in the MOSFET increased while the reverse substrate bias decreases in magnitude. Thus there exist extra dopants that are now included in the depletion region and may induce the threshold voltage fluctuation. This means that the mismatch in the body effect factor depends on back-gate bias. But what we focus on is the threshold voltage fluctuation attributed to a variation in the doping concentration, thus we can establish a threshold voltage fluctuation model of channel doping to estimate the random dopant effect on the threshold voltage fluctuation.
In order to derive the channel doping fluctuation model, we start from Eq. (7), parameters can be ignored, we can obtain:
2 2 2
, ,
Vth Vth dopant Vth others
(19)
where Vth others, are the other unknown parameters that influence the threshold voltage fluctuation. We substituting Eq. (18) to Eq. (14) , we can derive a threshold voltage fluctuation model of channel doping concentration [16]:
Here we still using the effective channel doping concentration extracted above. Fig.16 shows the results of calculated Vth dopant, by the model. By using Eq. (17), we can obtain the threshold voltage fluctuation effect due to the other unknown parameters as shown in Fig. 17. Based on these results, we can observe that the channel doping induced threshold voltage fluctuation is not obviously compared with other parameters, especially for the large device. But from the threshold voltage fluctuation model of channel doping concentration, we observe that when device size become more and more small with the technology advancement, channel doping concentration may become a more important factor of threshold voltage fluctuation.
In order to further discuss the effect of the random dopant, we take the boron clustering effect into consider [17],[18]. In this case, the charge of carrier q is replaced with nq and N is replaced with A NA/n . The threshold voltage is not change by these replacements as in the following:
( )( / ) into consider, the random dopant effect on threshold voltage fluctuation become more obviously. Fig.19 shows the Vth others, of different number of boron atoms per cluster
1 ~ 6
n . Therefore, the number of boron atoms per cluster must be taken into account while examining the threshold voltage fluctuation in the future.
Chapter 4
Mismatch Model Analysis and Modeling
4.1 Current Mismatch Model
It is widely known that the most important two parameters of mismatch are drain current and threshold voltage. Here we will connect them and derive a mismatch model in the following works. First, we define the current standard deviation as Id and threshold voltage standard deviation as Vth. We use statistics tool to calculate the mean and standard deviation of our experiment data. In the subthreshold region, the threshold voltage V affects the drain current th I through the following d Then we differentiate Eq. (23) and get:
Vth
deviation is always the positive value, Eq. (24) can be applied with the absolute value at both side. Since we can easily combine above-mentioned functions and build up a mismatch model of current and threshold voltage [19]:
( / ) deviation of threshold voltage and drain current. Now we take them into this model, assuming that the subthreshold swing mismatch is negligible here. The following are the results of using our experiment to fit this model. Fig. 20 shows the result of our experimental data at zero back-gate bias condition by using this model. From the correlation, it can be found that the difference between the model and experimentally extracted values are quite small.
4.2 Discussion of Current Mismatch Model
To make further use of this model, we observed that we can easily estimate the standard deviation of threshold voltage with only the standard deviation of drain current and subthreshold swing, and the result is worth being trusted. Eq. (28) can be rewritten as follows:
Fig. 21 shows the comparison between the calculated result and the experiment, thus confirming the validity of model. While this mismatch model has great estimation of the fluctuation, there are two points that should be mentioned. First, this model is just available in subthreshold region because it was derived from the subthreshold current
formula. Second, the applied current mismatch for different gate voltages might affect the slope of the fit-line because the current mismatch changes with applied gate voltage. Thus, besides the two points we mentioned-above, we can utilize this model with ease.
We have extensively measured the n-type device over a small back-gate bias range having different drawn gate widths and lengths. Experiment has exhibited that the significant drain current mismatch occurs in weak inversion, especially for small size devices. An analytic mismatch model has been developed and successfully reproduced the extensively measured data. With the aid of this model, threshold voltage mismatch can be expressed as a function of the process parameters, namely the subthreshold swing and current variation. Examples have been given to demonstrate that the model is capable of serving as a quantitative design tool for the optimal design between the mismatch criterion and device size.
Chapter 5 Conclusion
At first, we have addressed the advantages and disadvantages of operating MOSFETs in the subthreshold region, along with the discussions from different aspects. Due to many related researches of mismatch, we have found that there are two important characteristics of mismatch. One is process parameters that might followed the inverse square root of the device area and the other is the back-gate forward bias that might reduce the mismatch of the device.
Next, we have discussed the extraction of mismatch parameters. We have obtained several important parameters including the threshold voltage, the drain-induced barrier lowering, and the subthreshold swing. We have constructed a new model to explain that the threshold voltage increases with the channel length decrease and have confirmed it by experiment. After these parameters have been extracted, we have further established the mismatch model. We have reproduced with this model by the threshold voltage data and have made further discussions about the influence of the random dopant and boron clusters. Finally, we have derived a useful current mismatch model which can easily estimate the threshold voltage fluctuation from the drain current mismatch in subthreshold region. The schematic flowchart to summarize the procedure of our works is shown in Fig. 22.
Mismatch is indeed more and more important today, and our work is just a little step in this direction. It is expected that our studies and the models might be helpful for the future research.
References
[1] A. Pavasovic, “Subthreshold Region MOSFET Mismatch Analysis and Modeling for Analog VLSI Systems,” Ph. D. Dissertation, the Johns Hopkins University, 1991.
[2] E. A. Vittoz, “Micropower techniques”, in Design of MOS VLSI Circuits for Telecommunications, Y. Tsividis and P. Antognetti, Eds., Prentice-Hall, Inc., NJ. pp.
[2] E. A. Vittoz, “Micropower techniques”, in Design of MOS VLSI Circuits for Telecommunications, Y. Tsividis and P. Antognetti, Eds., Prentice-Hall, Inc., NJ. pp.