Chapter 4 Mismatch Model Analysis and Modeling
4.2 Discussion of Current Mismatch Model
deviation of threshold voltage and drain current. Now we take them into this model, assuming that the subthreshold swing mismatch is negligible here. The following are the results of using our experiment to fit this model. Fig. 20 shows the result of our experimental data at zero back-gate bias condition by using this model. From the correlation, it can be found that the difference between the model and experimentally extracted values are quite small.
4.2 Discussion of Current Mismatch Model
To make further use of this model, we observed that we can easily estimate the standard deviation of threshold voltage with only the standard deviation of drain current and subthreshold swing, and the result is worth being trusted. Eq. (28) can be rewritten as follows:
Fig. 21 shows the comparison between the calculated result and the experiment, thus confirming the validity of model. While this mismatch model has great estimation of the fluctuation, there are two points that should be mentioned. First, this model is just available in subthreshold region because it was derived from the subthreshold current
formula. Second, the applied current mismatch for different gate voltages might affect the slope of the fit-line because the current mismatch changes with applied gate voltage. Thus, besides the two points we mentioned-above, we can utilize this model with ease.
We have extensively measured the n-type device over a small back-gate bias range having different drawn gate widths and lengths. Experiment has exhibited that the significant drain current mismatch occurs in weak inversion, especially for small size devices. An analytic mismatch model has been developed and successfully reproduced the extensively measured data. With the aid of this model, threshold voltage mismatch can be expressed as a function of the process parameters, namely the subthreshold swing and current variation. Examples have been given to demonstrate that the model is capable of serving as a quantitative design tool for the optimal design between the mismatch criterion and device size.
Chapter 5 Conclusion
At first, we have addressed the advantages and disadvantages of operating MOSFETs in the subthreshold region, along with the discussions from different aspects. Due to many related researches of mismatch, we have found that there are two important characteristics of mismatch. One is process parameters that might followed the inverse square root of the device area and the other is the back-gate forward bias that might reduce the mismatch of the device.
Next, we have discussed the extraction of mismatch parameters. We have obtained several important parameters including the threshold voltage, the drain-induced barrier lowering, and the subthreshold swing. We have constructed a new model to explain that the threshold voltage increases with the channel length decrease and have confirmed it by experiment. After these parameters have been extracted, we have further established the mismatch model. We have reproduced with this model by the threshold voltage data and have made further discussions about the influence of the random dopant and boron clusters. Finally, we have derived a useful current mismatch model which can easily estimate the threshold voltage fluctuation from the drain current mismatch in subthreshold region. The schematic flowchart to summarize the procedure of our works is shown in Fig. 22.
Mismatch is indeed more and more important today, and our work is just a little step in this direction. It is expected that our studies and the models might be helpful for the future research.
References
[1] A. Pavasovic, “Subthreshold Region MOSFET Mismatch Analysis and Modeling for Analog VLSI Systems,” Ph. D. Dissertation, the Johns Hopkins University, 1991.
[2] E. A. Vittoz, “Micropower techniques”, in Design of MOS VLSI Circuits for Telecommunications, Y. Tsividis and P. Antognetti, Eds., Prentice-Hall, Inc., NJ. pp.
104-144, 1985.
[3] A. Papoulis, Probability, Random Variable and Stochastic Process, Kogakusha, Tokyo:McGraw-Hill,1965.
[4] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol.24, pp. 1433-1440, October 1989.
[5] M. J. Chen, J. S. Ho, and T. H. Huang, “Dependence of Current Match on Back-gate Bias in Weakly Inverted MOS Transistors and It’s Modeling,” IEEE J.
Solid-State Circuits, vol. 31, pp. 259-262, 1996.
[6] A. Ortiz-Conde, F.J. García Sánchez, J.J Liou, A.Cerdeira, M. Estrada and Y. Yue,
“A Review of Recent MOSFET Threshold Voltage Extraction Methods,”
Microelectronics Reliability, pp. 583-596, 2002.
[7] M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch and M. Hirose,
“Physically-based Threshold Voltage Determination for MOSFET’s of All Gate Lengths. IEEE Trans. Electron Device, vol. 46, pp. 1429-1434, 1999.
[8] Betty Lise Anderson and Richard L. Anderson, Fundamentals of Semiconductor Devices, McGraw-Hill, New York, International edition, 2005.
[9] Asen Asenov and Subhash Saini, “Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100nm MOSFET’s with Ultrathin Gate Oxide,” IEEE Trans. Electron Device, vol. 47, pp. 805-812, 2000.
[10] Asen Asenov, “Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 m MOSFET’s: A 3-D “Atomistic” Simulation Study,” IEEE Trans. Electron Device, vol. 45, pp. 2505-2513, 1998.
[11] Asen Asenov, “Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness,” IEEE Trans. Electron Device, vol. 50, pp.
1254-1260, 2003.
[12] Yiming Li, Shao-Ming Yu and Hung-Ming Chen, “Process-Variation-and Random-Dopants-Induced Threshold Voltage Fluctuations in Nanoscale CMOS and SOI devices,” Microelectronic Engineering, vol. 84, pp. 2117-2120, 2007.
[13] Yiming Li, Chih-Hong Hwang and Hui-Wen Cheng, "Process-Variation-and Random-Dopants-Induced Threshold Voltage Fluctuations in Nanoscale Planar MOSFET and Bulk FinFET Devices," Microelectronic Engineering, vol. 86, no. 3, pp.
277-282, 2009.
[14] K. Takeuchi, T. Tatsumi and A. Furukawa “Channel Engineering for The Reduction of Random-Dopant-Placement-Induced Threshold Voltage Fluctuation,”
IEDM 97, pp. 841-844, 1997.
[15] K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra,A Nishida, S. Kamohara, and T. Hiramoto, “Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies,” in IEDM Tech, pp. 467-470, 2007.
[16] Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, and Herman E. Maes, “An Easy-to-Use Mismatch Model for the MOS Transistor,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp.1056-1064, 2002.
[17] T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. in Kamohara, K.Terada, T. Hiramoto, and T. Mogami, “Analysis of 5 Vth Fluctuation 65nm-MOSFETs Using Takeuchi Plot,” VLSI Symp. Tech. Dig., pp. 156-157, 2008.
[18] Takaaki Tsunomura, Akio Nishida, and Toshire Hiramoto, “Analysis of NMOS and PMOS Difference in VT Variation with Large-Scale DMA-TEG,” IEEE Trans.
Electron Device, vol. 56, pp. 2073-2080, 2009.
[19] Pietro Andricciola and Hans P. Tuinhot, “The Temperature Dependence of Mismatch in Deep-Submicrometer Bulk MOSFETs,” IEEE Electron Device Letters, vol. 30, no.6, pp. 690-692, 2009.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-9
10-8 10-7 10-6
VBS=0.4(V) VBS=0(V) VBS=-0.4(V) VBS=-0.8(V) I D(A)
Vg(V)
W=1m L=1m Vd=0.01V
Fig.1 The measurement ID mean and standard deviation in both subthreshold region and above-threshold region with different back-gate biases.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-7
10-6 10-5
I D(A)
VG(V)
VBS= 0.4V VBS= 0V VBS=-0.4V VBS=-0.8V W=1m L=0.065m Vd=0.01V
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-7
10-6 10-5
I D(A)
VG(V)
VBS=0.4V VBS=0V VBS=-0.4V VBS=-0.8V W=0.6m L=0.065m Vd=0.01V
Fig. 2 The measured drain current versus gate voltage characteristics with different back-gate biases.
Fig. 3 Using constant current method to determine the threshold voltage in subthreshold region.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
10-8 10-7 10-6
VBS=0(V) Vd=0.01(V) I D*(L m/W m)(A)
VG(V)
The current we have chosen
Vth of specific one
Fig. 4 Measured mean threshold voltage with standard deviation versus the channel
Fig. 5 The measured subthreshold swing versus gate length for different gate widths.
0.0 0.2 0.4 0.6 0.8 1.0
75 80 85 90 95 100 105 110
Subthreshold swing(mV/decade)
L(m)
W=10(m) W=1(m) W=0.6(m) W=0.24(m) W=0.13(m) Vd=0.01V VBS=0V
0.0 0.2 0.4 0.6 0.8 1.0
0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22
Mean V th1(V)
L(m)
W=10m W=1m W=0.6m W=0.24m W=0.13m
Fig. 6 Measured mean threshold voltage versus L for different channel widths for Vd 1V.
0.0 0.2 0.4 0.6 0.8 1.0 0
50 100 150 200 250 300
Mean DIBL(mV/V)
L(m)
W=10m W=1m W=0.6m W=0.24m W=0.13m
Fig. 7 Extracted DIBL versus L for different channel widths.
0 2 4 6 8 10 12
0 5 10 15 20 25 30 35 40
DIBL standard deviaion(mV/V)
1/(WL)1/2(m-1)
Fig. 8 The measured DIBL standard deviation versus the inverse square root of the device area.
Fig. 9 The measured and calculated V standard deviation versus the inverse th1 square root of the device area.
0 2 4 6 8 10 12
0 10 20 30 40 50
model exp
Vth1(mV)1/(WL)1/2(m-1)
Fig. 10 The schematic drawing of halo doping device.
Fig. 11 The flat band voltage versus channel width at L=1m.
0.1 1 10
-0.7 -0.8 -0.9 -1.0
V FB(V)
W(m)
L=1m VBS=0V Vd=0.01V
NA_eff(cm-3) W=10 (m)
W=1 (m)
W=0.6 (m)
W=0.24 (m)
W=0.13 (m) L=1(m) 4.00E+17 4.00E+17 4.00E+17 4.00E+17 4.00E+17 L=0.5 (m) 5.92E+17 4.96E+17 5.04E+17 4.81E+17 5.05E+17 L=0.1 (m) 1.13E+18 1.16E+18 1.15E+18 1.12E+18 1.05E+18 L=0.065(m) 1.09E+18 1.16E+18 1.30E+18 1.44E+18 1.35E+18
Fig. 12 The extracted NA eff_ of all device sizes.
Fig. 13 Comparison of the Vth extracted from NA eff_ and the experimental data.
Fig. 14 Using measured data based on the fluctuation model to show the results of all device sizes for different back-gate biases.
VBS=-0.8V
0 2 4 6
VBS=-0.4V VBS=0V
0 2 4 6
0 5 10 15 20 25 30 35 40
VBS=0.4V
Vth(mV)(tox(Vth-VFB-2
f)/WL)1/2(nm1/2V1/2/m)
0 2 4 6 8 10 12
0 5 10 15 20 25 30 35 40
VBS=-0.8V AVth=3.93 (mV*m) VBS=-0.4V AVth=3.87 (mV*m) VBS=0V AVth=3.70 (mV*m) VBS=0.4V AVth=3.43 (mV*m)
Vth (mV)1/(WL)1/2(m-1) Vd=0.01V
Fig. 15 The measured standard deviation of threshold voltage difference versus the inverse square root of the device area for different back-gate biases.
0 2 4 6 8 10 12
0 2 4 6 8 10
VBS=-0.8V VBS=-0.4V VBS= 0V VBS= 0.4V
Vth,dopant(mV)1/(WL)1/2(m)
Fig. 16 The calculated Vth dopant, versus the inverse square root of the device area for different back-gate biases.
40
0 2 4 6 8 10 12 0
5 10 15 20
n=6 n=5 n=4 n=3 n=2 n=1
Vth,dopant(mV)1/(WL)1/2(m-1) VBS=0V
Fig. 18 The Vth dopant, with different number of boron atoms per cluster versus the inverse square root of the device area for zero back-gate bias.
Fig. 19 The Vth others, with different number of boron atoms per cluster versus the inverse square root of the device area for zero back-gate bias.
0 2 4 6 8 10 12
0 5 10 15 20 25 30 35 40
n=1 n=2 n=3 n=4 n=5 n=6
Vth,others(mV)1/(WL)1/2(m-1)
0.0 0.2 0.4 0.6 0.8 1.0
0 5 10 15 20 25
vth/n(mV)
ID/meanID
Id@Vgs-Vth~-0.1V VBS=0(V)Correlation:0.9409 Slope=25.43(mV)
Fig. 20 The experimental data and fitting line from the drain current and threshold voltage mismatch model.
Fig. 21 The standard deviation of threshold voltage from model and experiment.
0 2 4 6 8 10 12
0 5 10 15 20 25 30 35 40
Id@Vgs-Vth~-0.1VModel Exp. data
Vth(mV)1/(WL)1/2(m-1)
Fig. 22 The schematic flowchart for the procedure used in our works.