Without n+-LDD region at drain side, the decrease with the gate to drain capacitance and the gate to source capacitance. In addition, the depletion layer become longer, the resistance from gate to drain become larger.
Fig.3.4.
Fig. 3.4 Asymmetric LDD NMOS model (a) The BSIM model of A-LDD NMOS (b) The equivalent circuit of A-LDD NMOS
Chapter 4
Power Amplifier Design 4.1 Circuit design
In this work, the two-stage circuit has been used to realize a power amplifier. The power amplifier separates into drive stage and power stage. And the drive stage and the power stage operate in class A. The simplified schematic of the circuit is shown in Fig. 4.1.
Fig. 4.1 Schematic of the two stage amplifier circuit
For the power efficiency issue, we use the ratio of size for power stage and driver
MOS transistor has been used in PA design. The unit cell of asymmetric-LDD MOS transistor designed in this work has 0.18 μm gate-length, 5 μm width, and 10 gate fingers. And asymmetric-LDD MOS transistors have been implemented by foundry standard 0.18μm 1P6M process with only one additional mask but without process modification.
4.2 Design flow
For the design of power amplifier, there are some points that must be considered.
Such as supply voltage, frequency range, s-parameters, stability, gain, output power, input power levels, linearity and efficiency. So the first step of design, we have to determine the goal. Then use some methods to reach the goal. When the goal is determined, we choose the operating type and the bias point. Then we use the ideal lumped elements to design the input, internal, and the output matching network with some adjustment. After this, we replace the ideal lumped elements with TSMC model.
The design procedure of the amplifier has been carried out through the iteration of ADS and EM simulation. The design flow chart is shown in Fig. 4.2.
Fig. 4.2 Design flow chart
4.3 Pre-layout simulation
In this work, the goal we want to reach is shown in Table 4.1.
Operating type Class A
Frequency range 2.4GHz
Supply voltage 3V
S11 <-10dB
Power gain >20dB
Output P1dB >24dBm
PAE @ P1dB >20%
OIP3 >40dBm
Table 4.1 The goal of power amplifier
The architecture we use for the power amplifier is just like Fig. 4.1. The transistors in the power amplifier are asymmetric-LDD MOS transistors that introduce in chapter 3. And all of the transistors have 0.18 μm gate-length, 5 μm width, and 10 gate fingers.
For gate bias, the voltage we use in the drive stage and the power stage are both 1 V.
And we add inductor to get the result of RF choke and matching.
For drain bias, we use 3 V. And we add inductor to get the result of RF choke and matching.
For stability, we add resistor at gate and inductor at source to improve it.
So we can draw the schematic like Fig. 4.3.
Vinput
Fig. 4.3 schematic
Then we need to design the matching network. For the input matching network and the inter-stage matching network, we use conjugate matching to get the maximum gain. We use the Smith Chart to design like Fig. 4.4.
Fig. 4.4 Smith Chart for matching network
After matching, we can get the new schematic like Fig.4.5.
Vload
Then we need to design the output matching network. For a power amplifier, the power is very important. So we must design the output matching network to get the maximum power. Here we use the load-pull method in ADS to design. Load-pull is a method that can find out the impedance of the best power and the best efficiency in Smith Chart, shown in Fig. 4.6 and Fig. 4.7.
Fig. 4.6 Schematic of load-pull in ADS
Fig. 4.7 Simulation result of load-pull in ADS The simulation result of load-pull in this work is shown in Fig. 4.8.
indep(PAE_contours_p) (0.000 to 45.000)
PAE_contours_p
m1
indep(Pdel_contours_p) (0.000 to 39.000)
Pdel_contours_p
m2
m1 indep(m1)=
PAE_contours_p=0.529 / 172.854 level=27.463902, number=1 impedance = Z0 * (0.309 + j0.056)
2 m2
indep(m2)=
Pdel_contours_p=0.700 / -172.535 level=26.730701, number=1 impedance = Z0 * (0.177 - j0.063) m2 4
indep(m2)=
Pdel_contours_p=0.700 / -172.535 level=26.730701, number=1 impedance = Z0 * (0.177 - j0.063)
4 m1
indep(m1)=
PAE_contours_p=0.529 / 172.854 level=27.463902, number=1 impedance = Z0 * (0.309 + j0.056)
2
We can get the impedance for power (blue) and efficiency (red) from Fig. 4.8. We select the point near these two centers of a circle, accord with the goals of power and efficiency at the same time.
After repeated matching, we get the power amplifier with ideal lumped elements.
Then we replace the ideal lumped elements with TSMC model. And after tuning, we get the final power amplifier. The schematic is shown as follow.
Vload
Fig. 4.9 Ideal lump schematic
Vinput
Type=P+ Poly w/i silicide (0.18<=w<=5.0)(RF)
V_DC
Type=P+ Poly w/i silicide (0.18<=w<=5.0)(RF) C
Fig. 4.10 TSMC model schematic
The simulation results are shown as follow.
2 4 6 8
Fig. 4.11 S-parameter of pre-layout simulation
2 4 6 8
StabFact1 m12
m9
Fig. 4.12 Stability factor of pre-layout simulation
-15 -10 -5 0 5 10 15
plot_vs(Gain, Pin)=25.767-20.000 m15
indep(m15)=
plot_vs(Gain, Pin)=24.7311.500
-15 -10 -5 0 5 10 15
-20 20
10 15 20 25
5 30
Pin
Pout
m10 m10indep(m10)=
plot_vs(Pout, Pin)=26.2311.500
Fig. 4.14 Output power of pre-layout simulation
-15 -10 -5 0 5 10 15
-20 20
10 20 30 40 50
0 60
Pin
PAE m16
m16indep(m16)=
plot_vs(PAE, Pin)=23.2461.500
Fig. 4.15 Power Added Efficiency of pre-layout simulation
-15 -10 -5 0 5 10 15
-20 20
-60 -40 -20 0 20
-80 40
Pin
Spectrum[1]Spectrum[3]
Fig. 4.16 IP3 of pre-layout simulation
The layout has to be modified after post layout simulation.
4.4 Post-layout simulation
The critical DC power line generates parasitic resistance. To prevent loss, the line has to be widened. After modify the layout simulate the circuit again and find the best layout topology.
Fig. 4.17 Export the line of layout to momentum ADS system and simulation
Fig. 4.18 Post-layout simulation with line calculation
Modify the layout with better simulation result. Then determinate the best layout topology and tape out. With the simulation, the final layout is shown in Fig.4.19.
Fig. 4.19 The layout after post-layout simulation
The post-layout simulation results are shown as follow.
2 4 6 8
Fig. 4.20 S-parameter of post-layout simulation
2 4 6 8
Fig. 4.21 Stability factor of post-layout simulation
-15 -10 -5 0 5 10 15
-20 20
10 15 20 25
5 30
Pin
Gain
m14 m15
m14indep(m14)=
plot_vs(Gain, Pin)=26.559-20.000 m15
indep(m15)=
plot_vs(Gain, Pin)=25.474-0.500
Fig. 4.22 Power gain of post-layout simulation
-15 -10 -5 0 5 10 15
-20 20
10 15 20 25
5 30
Pin
Pout
m10
m10 indep(m10)=
plot_vs(Pout, Pin)=24.974 -0.500
-15 -10 -5 0 5 10 15
-20 20
10 20 30 40 50
0 60
Pin
PAE
m16
m16 indep(m16)=
plot_vs(PAE, Pin)=20.032 -0.500
Fig. 4.24 Power Added Efficiency of post-layout simulation
-15 -10 -5 0 5 10 15
-20 20
-60 -40 -20 0 20
-80 40
Pin
Spectrum[1]Spectrum[3]
Summary of post-layout simulation is shown in Table 4.2.
S11 -16.5dB
Power gain 26.5dB
Output P1dB 24.9dBm
PAE @ P1dB 20%
OIP3 >40dBm
Table 4.2 The result of power amplifier
From Table 4.2, we can see the result is up to specification.
4.5 Measurement
For this work, the inductor of matching network is off chip. But there are some mistakes on design, so the chip is not work. The photograph of the chip is shown in Fig. 4.26.
Fig. 4.26 The photograph of the chip
Chapter 5 Conclusion
We have designed an asymmetric-LDD MOS transistor which has twice drain breakdown voltage to the conventional one. Besides, the power amplifier has been designed by single ended and fabricated by TSMC 0.18μm 1P6M process without any process modification.
According to simulation, this power amplifier can achieve 26.5dB power gain, 24.9dBm output P1dB, and 20% PAE at P1dB.
This research demonstrated that the asymmetric-LDD MOS transistor successfully implemented on a CMOS power amplifier with wonderful performance. This design method has great opportunity to be future trend.
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