From the observations of S-parameters after HC stress, we assume that there are no new components added to the equivalent circuit shown in Fig. 5-1.Therefore, we directly use conventional small-signal model to establish the device model under HC stress. As shown in Fig.
5-6, this model is accurate under HC stress. Table 5-1 shows the extracted parameters of this study structure before and after HC stress on condition B and condition C. We found that only Cgs, gm0, Rds and Rd suffer degradations obviously after HC stress.
First of all, we plot the extracted Cgs and Cgd with increasing stress time, as shown in Fig.5-7 and Fig.5-8. It is obvious that Cgs increase in HV01 and HV02 with increasing HC stress time on condition B and condition C. The variations of Cgd are very slight compared with that of Cgs. We use the definition of small-signal gate-to-source capacitance to explain this observation [24]:
0
in which L and W are the length and width of the MOSFET, respectively, vac is the small signal potential along the channel, vsig is the small signal voltage applied to the source in order to measure Cgs, and Cox is the gate oxide capacitance per unit area. For fresh device, there are no negative trap charges near drain. Hence vac changes uniformly from source to drain terminal.
After HC stress, due to the presence of negative trap charges near drain, vac near drain increases.
Therefore the value of equation (5-14) increases and Cgs increases dramatically after HC stress. It implies that input matching has been changed at high frequency. It should be pointed out that depending on bias point, Cgd changes slightly, as confirmed by the data in [25]. As a result, the variation of Cgd is too small to have any significant effects on the RF performance of the MOSFET compared to that of Cgs.
Fig. 5-9 shows the degradations of gm0 of HV01 and HV02 with increasing stress time on condition B and condition C. The degradations of gm0 are more serious when biasing at lower gate voltages. And it direction is similarity to gm which be measured on DC characteristic.
5.3 Summary
From observing the small-signal model, the transconductance(gm0), drain-to-source resistance(Rds), gate-to-source capacitance(Cgs), and drain resistance(Rd) suffer more degradation after HC stress. Especially, the Rd was an important factor that was decision the divergence on structures of the HV01 and the HV02. Because Rd in HV01 was bigger than HV02 at the same Vgd, voltage dropped in the drain region occupied most voltage than the voltage dropped in the channel between gate to drain. Then the HV02 voltage dropped was occupied most in the channel.
Consequently, the reliability was badly in HV02 than in HV01. Finaly, we proved it again by
small-signal model.
HV01 Condition B Gm0(ms) τ(psec) Rg(Ω) Rs(Ω) Rd(Ω) Rds (Ω) Rsub(Ω)
Before Stress 113.4 2.8 4.441 2.43 6.7 93 60.12
After HC stress 96.36 2.8 4.441 2.4 7.5 96.5 60.12
HV01 Condition B Cgd(fF) Csub(fF) Cds(fF) Cjdb(fF) Cgs(fF)
Before Stress 44.27 26.3 23 220 125.7
After HC stress 45.1 26.3 23 220 132.6
Table 5-1 (a)
Table 5-1(a) Extracted parameters before and after HC stress condition B on HV01
HV02 Condition B Gm0(ms) τ(psec) Rg(Ω) Rs(Ω) Rd(Ω) Rds (Ω) Rsub(Ω)
Before Stress 118.8 2.8 4.441 2.32 4.82 94.52 34
After HC stress 98.9 2.8 4.441 2.3 5.48 98.61 34
HV02 Condition B Cgd(fF) Csub(fF) Cds(fF) Cjdb(fF) Cgs(fF)
Before Stress 48.08 26.6 23 368 122.6
After HC stress 48.46 26.6 23 368 128.1
Table 5-1 (b)
Table 5-1(b) Extracted parameters before and after HC stress condition B on HV02
HV01 Condition C Gm0(ms) τ(psec) Rg(Ω) Rs(Ω) Rd(Ω) Rds (Ω) Rsub(Ω)
Before Stress 113.5 2.8 4.441 2.4 6.72 97.6 59.5
After HC stress 103.3 2.8 4.441 2.37 7.18 89 59.5
HV01 Condition C Cgd(fF) Csub(fF) Cds(fF) Cjdb(fF) Cgs(fF)
Before Stress 45.24 25 27 216 131.6
After HC stress 46 25 27 216 135.2
Table 5-1 (c)
Table 5-1(c) Extracted parameters before and after HC stress condition C on HV01
HV02 Condition C Gm0(ms) τ(psec) Rg(Ω) Rs(Ω) Rd(Ω) Rds (Ω) Rsub(Ω)
Before Stress 118.7 2.8 4.441 2.3 4.81 95.7 36
After HC stress 106.6 2.8 4.441 2.3 5.2 87.55 36
HV02 Condition C Cgd(fF) Csub(fF) Cds(fF) Cjdb(fF) Cgs(fF)
Before Stress 48.48 29 24 357 116.2
After HC stress 48.54 29 24 357 119.2
Table 5-1 (d)
Table 5-1(d) Extracted parameters before and after HC stress condition C on HV02
Fig.5-1 (a)
Fig.5-1 (b)
Fig.5-1: (a) Conventional small-signal model of a MOSFET (b) Equivalent circuit after de-embedding parasitic components
Cds
-Fig.5-1 (c)
Fig.5-1(c) Small-signal model for the intrinsic part of a MOSFET
Fig.5-2 Conventional small-signal model for silicon MOSFET’s
Zo
0 10G 20G 30G 40G 50G 0
10 20 30 40
freq(Hz)
Resistance(o h m )
real(Z.12) real(Z.22-Z12) real(Z.11-Z12) Rs_fit
Rd_fit Rg_fit
Fig.5-3 Extracted values of Rs, Rg and Rd versus frequency
0 1G 2G 3G 4G 5G
0.0 5.0G 10.0G 15.0G 20.0G 25.0G 30.0G 95.00
Fig. 5-4: (a) Extracted gm0 versus frequency (b) Extracted Rds versus frequency
5.0G 10.0G 15.0G 20.0G 25.0G 30.0G 30.0f
60.0f 90.0f 120.0f 150.0f
Capacitance(F)
freq(HZ)
Cgd Cgs Cds Cgd_fit Cgs_fit Cds_fit
Fig. 5-4 (c)
Fig. 5-4: (c) Extracted capacitance versus frequency
Swp Min 50GHz
Swp Min 0.2GHz Measured
Simulated
S11
Swp Min 0.2GHz Swp Min 50GHz
S22
Measured Simulated
Fig. 5-5(a): Measured and modeled S-parameters of a MOSFET before stress at VG=1V VD=1.2V
S12
Measured Simulated
Swp Min 0.2GHz Swp Min
50GHz
S21
Measured Simulated
Swp Min 0.2GHz Swp Min
50GHz
Fig. 5-5(b): Measured and modeled S-parameters of a MOSFET before stress at VG=1V VD=1.2V.
Swp Min 50GHz
Swp Min 0.2GHz Measured
Simulated
S11
Swp Min 0.2GHz Swp Min
50GHz
S22
Measured Simulated
Fig. 5-6(a): Measured and Simulated S-parameters of a MOSFET after1000s HC stress
S12
Measured Simulated
Swp Min 0.2GHz Swp Min
50GHz
S21
Measured Simulated
Swp Min 0.2GHz Swp Min
50GHz
Fig. 5-6(b): Measured and Simulated S-parameters of a MOSFET after1000s HC stress
0 200 400 600 800 1000
Stress condition B (Vg=1.5V Vd=3V)
HV01
Stress condition C (Vg=3V Vd=3V)
HV01 HV02
Stress Time(s)
Fig. 5-7 (b)
Fig. 5-7: (a) Extracted Cgs degradation of HV01 and HV02 on condition B with increasing stress time(b) Extracted Cgs degradation of HV01 and HV02 on condition C with increasing stress time
0 200 400 600 800 1000
Stress condition B (Vg=1.5V Vd=3V)
HV01
Stress condition C (Vg=3V Vd=3V)
HV01 HV02
Stress Time(s)
Fig. 5-8 (b)
Fig 5-8: (a) Extracted Cgd degradation of HV01 and HV02 on condition B with increasing stress time (b) Extracted Cgd degradation of HV01 and HV02 on condition C with increasing stress time
0 200 400 600 800 1000
0 Stress condition B (Vg=1.5V Vd=3V)
HV14
0 Stress condition C (Vg=3V Vd=3V)
HV14 HV17
Stress Time(s)
Gm Degradation(%)
Fig. 5-9 (b)
Fig. 5-9: (a) Variations of Extracted gm0 with increasing HC stress time on condition B (b) Variations of Extracted gm0 with increasing HC stress time on condition C
Chapter 6
Conclusions
6.1 Conclusions
MOSFET are getting more and more important in current commercial market especially for the RF applications. In this thesis, we used a new power MOSFETs which was called PDMOS designed for RF power applications that relies on only layout scheme was investigated. It was success to improved the high frequency and power performance on traditions power MOS. And we also have established a conventional small-signal model for the MOSFETs under HC stress.
HCS reduce the transconductance, output drain current and enlarge threshold voltage of the MOSFET. Consequently, the high frequency and power characteristics will suffer degradation by those effects. In the first instance, we found that the cut-off frequency and maximum oscillation frequency all decreased after stress. Then the RF output power will suffer degradation after HCS and we find that the RF power and gain are more robust to HC effects by biasing the gate voltage to higher values. In this study, we discussed and compared two structures. The DC and RF characteristics on HV02 were better than HV01, caused the transconductance (gm) of HV02 was higher. After HC stress, we found that HV01 had superior reliability to against this external force.
Maybe the difference drain region of these two structures induced the result. Then we focused on the different HC stress conditions in the some device. The HC stress condition A and condition B had worse reliability to HC stress condition C.
Finally, from observing the small-signal model in chapter 5, the transconductance (gm0),
drain-to-source resistance (Rds), gate-to-source capacitance (Cgs), and drain resistance (Rd) degrade significantly after HC stress. We also observed that Rd was crucial factor on the PDMOS structure. And the small-signal model was success to support our contention.
The results achieved from the implementation of 0.13μm MOS RF power devices demonstrate the potential power amplification capability of CMOS technologies for future integrated RF applications
References
[1] F. Schwierz, Microwave Transistors: State of the Art in 1980s, 1990s, and 2000s. A Compilation of 100 Top References, TU Ilmenau 2002.
[2] F. Schwierz and J.J. Liou, Semiconductor Devices for Wireless Communications and High-Speed Internet, Proc. SSGRR-2000, pp. 331.1-10, 2000.
[3] F. Schwierz and J.J. Liou, Semiconductor Devices for RF Applications: “Evolution and Current Status”, Microelectron. Reliab, pp. 145-168, 2001.
[4] A. A. Abidi, “RF CMOS comes of age,” IEEE J. Solid-State Circuits., vol. 39, no. 4, pp.
549-561, April 2004
[5] Pierre H.Woerlee, Mathijs J. Knitel, “RF CMOS Performance Trends,” IEEE Trans.
Electron Devices, Vol 8, pp. 1778-1782,2001.
[6] E.Morifujiet al, “Future Perspective and Scaling Down Roadmap of RF CMOS”, Symposium of VLSI Circuits, pp. 165-166, 1999.
[7] Liou, J.J.; Schwierz, F, “RF MOSFET: Recent Advance and Future Trends” Electron Devices and Solid-State Circuits, pp. 185 – 192, 2003.
[8] H. Hara, Y. Okamoto and H. Ohnuma, “A New Instability in MOS Transistors Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide,”Japanese Journal of Applied Physics, Vol. 9, pp. 1103-1112, 1970.
[9] S. A. Abbas and R. C. Dockerty; “Hot-carriers instability in IGFET’s” Applied Physics Letter, Vol. 27, NO. 3, pp. 147-148, 1975.
[10] T.H. Ning, C. M. Osburn and H. N. Yu “Effect of Electron Trapping on IGFET Characteristics” Journal of Electronic Materials, Vol. 6, NO. 2, pp: 65-76, 1976.
[11] Qiang Li, Yuan Chen, “RF Circuit Performance Degradation Due to Soft Breakdown and Hot-Carrier Effect in Deep-Submicrometer CMOS Technology” IEEE Transcations on Microwave Theory and Techniques, Vol. 49, NO. 9, pp. 1546-1551, 2001.
[12] S. Tam, C Hu“Luck-Electron Model of Channel Hot Electrons Injection in MOSFETs IEEE Transactions on Electron Device, Vol. 31, NO. 9, pp. 1116-1125, 1984.
[13] E. Takeda, Y. Nakagome, H. Kumes,“A New Hot carrier Injection a Device Degradation in Submicron MOSFETs ＂ IEE Proceedings, Vol. 130, NO.3, pp.144-149,1983.
[14] S. M. Sze and Kwok K. Ng, “Physics of semiconductor devices” 3rd Edition, New York:
Wiley (2007)
[15] Taur Ning, “Fundamentals of Modern VLSI Devices” CAMBERIDGE, 1998, chapter 3.
[16] Sheng-Yi Huang, Kun-Ming Chen, Guo-Wei Huang, Chun-Yen Chang,“Novel Pseudo-Drain (PD) RF Power Cell in 0.13 um CMOS＂IEEE ,Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008.
[17] C. Y. Chang and S. M. Sze, “ULSI Devices,” Wiley Interscience, 2000. Chap 6.
[18] W.L. Ng and N. Toledo, “RF HCI testing methodology and lifetime model establishment,”
Reliability Physics Symposium Proceedings (IRPS), pp.1-3, 2004.
[19] Y. T. Yeow, C.H. Ling, “ Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement,” IEEE Electron Device Letters, Vol.12, pp366-369, 1991.
[20] S. Lee et al., “A small-signal RF model and its parameter extraction for substrate effects in RF MOSFET’s,” IEEE Trans. Electron Devices, vol. 48, pp. 1374–1379, 2001.
[21] S. C. Wang, G. W. Huang, “A Practical Method to Extract Extrinsic Parameters for the Silicon MOSFET Small-Signal Model” 2004 Workshop on Compact Modeling, 2004.
[22] S. Lee, H. K. Yu, C. S. Kim, “A novel approach to extracting small-signal model parameters ofsilicon MOSFET's,” IEEE, Microwave and Guided Wave Letters, 1997
[23] S. Lee, H. K. Yu, C. S. Kim, “A small-signal RF model and its parameter extraction for substrate effects in RF MOSFETs” Electron Devices, IEEE Transactions on, 2001
[24] Y. T. Yew, C. H. Ling, “Observation of MOSFET Degradation Due to Electrical Stressing Through Gate-to-Drain Capacitance Measurement,” IEEE Electron Device Letters, Vol.12,
NO.7, pp.366-368, 1991
[25] C. H. Ling, “A study of Hot Carrier Degradation in NMOSFET’s by Gate Capacitance and charge pumping method,” IEEE Transaction on Electron Device, Vol. 42, NO. 7, pp.
1321-1328, 1995.