The effect of HC stress on the output power of a MOS transistor is shown in Fig.4-9. It was measured at gate voltage VGS=1 V and drain voltage VDS =1.2 V, where gm is the maximum value in device saturation regions, and the frequency was operated at 2.4 GHz. The source and load impedances are matched for maximum output power before stress. The degradations of output power, power gain and power-added efficiency (PAE) are shown in Fig.4-9. The PAE can be expressed by:
At low input power, the PAE is less changed under stress, due to the output power and drain current, and thus power dissipation, reduce simultaneously. When input power is larger than 1dB compression point, the degradations of PAE become serious. Because a part of the ac signal of drain current will be cut off as the input power is large enough. For this reason, the average drain current will increase with increasing input power. Since the bias current of the device after HC
stress is lower than that of the fresh one, the negative duty cycle of output waveform would enter the cut off region earlier. As a result, the power dissipation of stressed device is higher than that of fresh one, leading to lower PAE. Since the DC degradation is more serious after DAHC stress, the degradations of PAE is more serious after DAHC stress.
To characterize the linearity which is showed in Fig.4-10 that the third-order intercept point (IP3), at which the output power and third-order intermodulation (IM3) power are equal, is commonly used. For low distortion operation, the third-order intercept point should be as high as possible. From Table.4-1, we can take notice of the RF linearity degrades under DAHC stress is more serious than CHE stress when the MOSFET operates at a fixed gate bias.
4.5 Summary
Compared to HV01, although HV02 had better DC characteristic, the RF and power characteristics were weakly after the same stress condition. Therefore, we could say HV01 has better reliability than HV02. Also, we compared the identical device under the different stress conditions, the HC stress condition B had worse reliability to HC stress condition C on the same device.
IIP3 (dBm) OIP3 (dBm)
Before Stress After stress Before Stress After Stress
condition B 4.74 4.4 18.42 17.43
HV01
condition C 5.03 4.77 19.14 18.72
condition B 5.36 4.8 18.87 17.22
HV02
condition C 5.45 5.08 19.05 18.64
Table.4-1: Extracted linearity parameters of HV01, HV02
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Fig. 4-1: (a) DC characteristics of HV01 before and after CHE stress (b) DC characteristics of HV02 before and after CHE stress
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Fig. 4-1: (c) DC characteristics of HV01 before and after DAHC stress (d) DC characteristics of HV02 before and after DAHC stress
0 100 200 300 400 500 Stress condition A (Vg=Vth+0.1V Vd=3V)
Stress Time(s)
Stress condition B (Vg=1.5V Vd=3V)
HV14 HV17
Stress Time(s)
Gm Degradation(%)
Fig.4-2 (b)
Fig.4-2 (a) To compare gm characteristics of HV01 and HV02 on Condition A with increasing stress time (b) To compare gm characteristics of HV01 and HV02 on condition B with increasing stress time
0 500 1000 1500 2000 -12
-10 -8 -6 -4 -2 0
Stress condition C (Vg=3V Vd=3V)
HV14 HV17
Stress Time(s)
Gm Degradation(%)
Fig.4-2 (c)
Fig.4-2 (c)To compare gm characteristics of HV01 and HV02 on condition C with increasing stress time
0 100 200 300 400 500 Stress condition A (Vg=Vth+0.1V Vd=3V)
Stress Time(s)
Stress condition B (Vg=1.5V Vd=3V)
HV14 HV17
Stress Time(s) I on Degradation(%)
Fig. 4-3 (b)
Fig. 4-3: (a) To compare Ion characteristics of HV01 and HV02 on condition A with increasing stress time (b) To compare Ion characteristics of HV01 and HV02 on condition B with increasing stress time
0 500 1000 1500 2000 -12
-8 -4 0
Stress condition C (Vg=3V Vd=3V)
HV14 HV17
Stress Time(s) I on Degradation(%)
Fig. 4-3 (c)
Fig. 4-3: (c) To compare Ion characteristics of HV01 and HV02 on condition C with increasing stress time
0 100 200 300 400 500 Stress condition A (Vg=Vth+0.1V Vd=3V)
V th Degradation
0.12 Stress condition B (Vg=1.5V Vd=3V)
HV01 HV02 Vth Degradation
Stress Time(s)
Fig.4-4 (b)
Fig.4-4 (a) To compare Vth characteristics of HV01 and HV02 on condition A with increasing stress time(b) To compare Vth characteristics of HV01 and HV02 on condition B with increasing stress time
0 500 1000 1500 2000 0.00
0.02 0.04 0.06 0.08 0.10
0.12 Stress condition C (Vg=3V Vd=3V)
HV01 HV02
Stress Time(s) V th Degradation
Fig.4-4 (c)
Fig.4-4 (c) To compare Vth characteristics of HV01 and HV02 on condition C with increasing stress time
0 100 200 300 400 500
Stress condition A (Vg=Vth+0.1V Vd=3V)
R on Degradation(%)
Stress condition B (Vg=1.5V Vd=3V)
HV01 characteristics of HV01 and HV02 on condition B with increasing stress time
0 500 1000 1500 2000 0
10 20 30 40
Stress condition C (Vg=3V Vd=3V)
HV01 HV02
Stress Time(s) R on Degradation(%)
Fig.4-5 (c)
Fig.4-5 (c) To compare Ron characteristics of HV01 and HV02 on condition C with increasing stress time
0 200 400 600 800 1000
Fig. 4-6: (a) Cut-off frequency before and after HC stress on HV01 and HV02 (b) Maximum oscillation frequency before and after HC stress on HV01 and HV02
0 200 400 600 800 1000 HV01 and HV02 (b) Maximum oscillation frequency before and after HC stress on HV01 and HV02
5 10 15
Fig. 4-8: (a) Relation between fT and fmax degradations and gm degradation on condition B of HV01 (b)Relation between fT and fmax degradations and gm degradation on condition B of HV02
2 3 4
Fig. 4-8: (c) Relation between fT and fmax degradations and gm degradation on condition C of HV01 (d) Relation between fT and fmax degradations and gm degradation on condition C of HV02
-35 -30 -25 -20 -15 -10 -5 0 5 10
Output Power & Power Gain (dBm/dB)
Input Power(dBm)
Output Power & Power Gain (dBm/dB) Power Added Efficiency(%)
Input Power(dBm)
Fig. 4-9: (a) Output power, power gain and PAE versus input power before and after HC stress on condition B of HV01. (b) Output power, power gain and PAE versus input power before and after HC stress on condition B of HV02
-Fig. 4-10 (a)
Fig. 4-10 (b)
Fig. 4-10: (a) Output power and 3rd-order intermodulation (IM3) power versus input power before and after HC stress on condition B of HV01 (b) Output power and 3rd-order intermodulation (IM3) power versus input
power before and after HC stress on condition B of HV02
-35 -30 -25 -20 -15 -10
Output Power & IM3 (dBm/dB)
Input Power(dBm)
Output Power & IM3 (dBm/dB)
Input Power(dBm)
Chapter 5
Modeling of RF MOSFETs under HC stress
Introduction
In this chapter, we create a small-signal model of the RF MOSFET which is valid up to 50 GHz. An extraction approach, which was proposed by S. Lee [20], was adopted to determine the intrinsic circuit parameters. For modeling devices under HC stress, we compare the variations of each parameter after stress. And we use another method to model the substrate parasitic effect.
When the drain-side substrate parasitic is taken into account, careful attention must be taken into consideration, especially for RFIC applications.
5.1 Extraction Method of Small-Signal Model Parameters
The small-signal model shown in Fig. 5-1(a) can be partitioned into three parts. The first part includes the parasitic series resistors Rg, Rd and Rs, and the second part refers to as the substrate network. The third part is the intrinsic model. We extract the parasitic resistors by using the conventional small-signal equivalent circuit as shown in Fig. 5-2. If the frequency is not high enough, we can ignore the substrate network. Conversion of the measured S-parameters into real components of an equivalent z-parameters network yields the parasitic resistance values.
Equations for the parasitic resistances of the model shown in Fig. 5-2 are given by:
12 2
Re(Z )=Rs+ As
w +B (5-1)
11 12 g 2
Fig. 5-3 illustrates the values of Rg, Rd and Rs extracted by this technique. After de-embedding the parasitic parameters, we use the curve-fitting method [21][22][23] to extract the parameters associated with the substrate parasitic. After d-embedding Rg, Rs, and Rd, the resulting network would become that shown in Fig. 5-1(b) and it will produce following equations:
2
where k1, k2, m1, m2 can be considered as constants. From above equations, the parameters which are associated with substrate network can be obtained by using curve-fitting method.
Finally the parameters of the intrinsic network shown in Fig. 5-1(c) can be directly extracted by following equations [21],[22],[23]:
,22
Fig. 5-4 shows the extracted values of each parameter versus frequency. The extracted parameters remained somewhat constant with frequency. Finally we show the measured and modeled S-parameters in Fig. 5-5 to verify the accuracy of this model.