The major research subject of this thesis is Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si), which has been widely employed to fabricate low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs). However, the high leakage current is an annoying issue of MIC TFTs because Ni residues trapped inside the MIC poly-Si films.
The Ni residues could be reduced by gettering method or metal-induced crystallization through a cap layer (MICC). Gettering method was an efficient technology to capture Ni residues from poly-Si, but the process was complex and the on-state current of poly-Si films decreased. MICC used a SiNx cap layer to reduce Ni diffusion into poly-Si film, however that still needed high temperature and long annealing time, and the Ni degree of reduction is not Fig. 1- 6 The band diagram for the leakage current model. (a) Case of weak electric field. (b)
Case of medium electric field. (c) Case of strong electric field.
conspicuous. Besides, these two methods need extra expensive and complicated vacuum instrument. However, both methods are complex and incur high cost. Additionally, a hydrogen plasma treatment process has been utilized to eliminate the trap states of poly-Si film to improve the on-state current. However, the hydrogen concentration in the poly-Si film was hard to control, and the formed Si-H bonds were too weak to resist the hot carrier generation. Therefore, the main purpose of this thesis is to reduce Ni residues, to improve electrical performance of MIC TFTs, and further to investigate the effects of Ni concentration on others of importantly electrical characteristics.
The thesis is divided into five chapters listed following:
In chapter 1, overview of low temperature polycrystalline silicon TFT technology is reviewed, then the processes of low temperature crystallization of amorphous silicon, Issues of polycrystalline silicon films, and electrical characteristics of Ni-metal induced crystallization (MIC) TFTs. Finally, the motivation of this study and the outline of the dissertation are provided.
In chapter 2, a chemical oxide filter layer was introduced into MIC processes to reduce the Ni residues in poly-Si films, which was simple and without extra expensive instrument.
The optimum thickness of chemical oxide layer in Ni reduction was extracted to fabricate TFT devices. Moreover, the electrical performance of MIC TFTs with and without chemical oxide was investigated.
In chapter 3, effect of Ni concentration on electrical characteristics of MIC TFTs was studied, including source/drain (S/D) series resistance, bias reliability and thermal stability. In this work, the transmission line method (TLM) test structure is employed to measure the S/D series resistance of a top-gate TFT device used to induce electrons into the channel. Moreover, the bias reliability and thermal stability was investigated under hot carrier condition and high temperature environment. The results of this chapter proved that how reducing Ni concentration affected the S/D series resistance, bias reliability and thermal stability.
In chapter 4, a new manufacturing method for poly-Si TFTs using drive-in Ni induced crystallization (DIC) was proposed to reduce Ni concentration and minimize the trap-state density. In DIC, F+ implantation was used to drive Ni in the α-Si layer. To further improvement, a cap oxide layer was introduced into DIC process (DICC) to reduce ion implant damages. Simultaneously, bias reliability was also studied by using the hot-carrier stress.
In chapter 5, conclusions and future works are summarized respectively.
Chapter 2
Reduced Leakage Current of Nickel Induced Crystallization Poly-Si TFTs by a Simple Chemical
Oxide Layer
2.1 Introduction
Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have attracted considerable interest for high resolution integrated active-matrix liquid crystal displays (AMLCDs) and active-matrix organic light-emitting diodes (AMOLED) because they exhibit good electrical properties and can be used in the realization of system-on-glass (SOG) [47]-[48]. Intensive studies have been carried out to lower the crystallization temperature of amorphous silicon (α-Si) films. The solid phase crystallization (SPC) method is a well-established poly-Si formation technique [49]. The major drawback of SPC is that the α-Si films need to be annealed for about 24 h at 600°C, which is higher than the strain temperature of a normal glass substrate. In contrast, metal induced crystallization (MIC) and metal induced lateral crystallization (MILC) methods require a lower thermal budget and present a great on-state of electrical performance than SPC [40], [50], [51].
crystallize at a temperature below 600°C. Unfortunately, the uniformity is poor, annealing time is long, and extra mask is needed to define the Ni window. In contrast, MIC method is much simple for commercial manufacturing. No extra mask is needed, the annealing time is short (0.5 - 5 h), and the uniformity is good. Compared with various metal, Ni-MIC process produces crystallized α-Si thin films of the best quality because NiSi2 has the lowest lattice mismatch (0.4%) with Si [50]-[51] Unfortunately, Ni and NiSi2 residues in the poly-Si film increased the leakage current and shifted the threshold voltage [52]-[53]. The Ni residues could be reduced by gettering method or metal diffusion filter layer (MICC). Gettering method was an efficient technology to capture Ni residues from poly-Si, but the process was complex and the on-state current of poly-Si films decreased [54]. MICC used a SiNx cap layer to reduce Ni diffusion into poly-Si film, however that still needed high temperature and long annealing time, and the Ni degree of reduction is not conspicuous [55]-[56]. Besides, these two methods need extra expensive and complicated vacuum instrument.
In this study, a simple chemical oxide layer was introduced between α-Si layer and Ni layer to avoid excess of Ni atoms into α-Si layer during MIC process. The manufacture processes were very simple and without extra expensive instrument. It was found that the minimum leakage current of poly-Si TFTs was greatly reduced.
2.2 Experimental procedure
N-channel poly-Si TFTs were investigated in this study. Figure 2-1 shows Schematic diagrams of process flow of chemical oxide filter MIC TFTs (CF-MIC). A 100-nm-thick undoped α-Si layer was deposited onto a 500-nm-thick oxide-coated Si wafer by low pressure chemical vapor deposition (LPCVD) system. To form chemical oxide MIC poly-Si, samples were dipped into a chemical solution of 3H2SO4 : 1H2O2 for 20 min to form a chemical oxide filter layer on the top of α-Si. A 5-nm-thick Ni film was then deposited and subsequently annealedat 500°C for 1 h in N2 for crystallization of α-Si. The unreacted Ni film and chemical oxide layer were then removed by wet etching.
The islands of poly-Si regions on the wafers were defined by Reactive ion etching (RIE).
After cleaning process, a 100-nm-thick tetraethylorthosilicate/O2 (TEOS) oxide layer was deposited as the gate insulator by plasma-enhanced chemical vapor deposition (PECVD).
Then a 100-nm-thick poly-Si film was deposited as the gate electrode by LPCVD. After defining the gate, self-aligned 35 keV phosphorous ions were implanted at a dose of 5 × 1015 cm-2 to form the source/drain and gate. The dopant activation was performed at 600°C for 24 h. A 500-nm-thick TEOS oxide layer was deposited as the passivation layer by PECVD, followed by a definition of contact holes. A 500-nm-thick Al layer was then deposited by thermal evaporation and patterned as the electrode. Finally, sintering process was performed at 400°C for 30 min in N2 ambient.
It is worthy to note that this CF-MIC process does not need any additional annealing step and expensive vacuum equipment, and is compatible with conventional MIC processes.
For the purpose of comparison, solid phase crystallization (SPC) TFTs, and conventional MIC TFTs without chemical oxide layer were also fabricated under the same conditions.
Fig. 2-1 Schematic diagrams of process flow of MIC TFTs with chemical oxide filter layer.
2.3 Results and discussion
2.3.1 Characterization of chemical oxide layer
The transmission electronic microscopy (TEM) cross-section image of chemical oxide layer was shown in Fig. 2-2. To examine the quality of chem-SiO2, after the chem-SiO2 layer was formed, platinum was deposited on top of the chem-SiO2 for image contrast in TEM sample preparation. A relation of chemical oxide thickness versus immersed time was also investigated by TEM. As shown in Fig. 2-3, the chemical oxide growth controlled by diffusion of reactants through the pre-existing layer conformed to the model of oxide growth.
The growth kinetic could be well represented with the expression (1) for the short time:
d = E ln ( 1 + Ft ) (1) where E and F are adjusted parameters proportional to the penetration depth of the species and to the concentration of the precursors, respectively [57]. In this work, there is an approximately saturation thickness of 3.4 nm after dipped for 10 min. For this reason, it is easy to achieve the same result when samples immersed into a chemical solution of 3H2SO4 : 1H2O2 over 10 or 15 min. For purposed comparison, the stable parameter at 20 min of immersed time was chosen to investigate with conventional MIC, subsequently.
Fig. 2-3 Formation thickness of chemical oxide layer versus immersed time.
Fig. 2-2 TEM cross-section image of chemical oxide layer after dipped for 20 min. Platinum film deposited on the top of the chem-SiO2 layer was for the TEM sample preparation.
Figure 2-4 shows X-ray photoelectron spectroscopy (XPS) of Si2p peak for the chemical oxide on top of α-Si layer with 20 min dipping. Black line is the raw data and the other lines were obtained by the curve-fitting calculation. According to the detailed XPS studies of surface oxidation layer of Si, it was observed Si, SiO and SiO2 peaks are located at binding energy of 99.6, 101.7 and 103.2 eV, respectively [58]-[60]. We believe that the signal of Si peak was obtained from the bottom layer (α-Si) because the thickness of chemical oxide layer is less than XPS sampling depth. Therefore, it can be clear to define that the chemical oxide is composed of SiO and SiO2.
Fig. 2-4 X-ray photoelectron spectroscopy (XPS) of Si2p peak for the chemical oxide on top of α-Si layer.
2.3.2 Reduction of Ni concentration in MIC poly-Si films
To investigate the effect of chemical oxide on the reduction of Ni residues, samples were purposely dipped into a silicide-etching solution (HNO3:NH4F:H2O = 4:1:50) after unreacted Ni film and chemical oxide layer were removed. As shown in Fig. 2-5, numerous holes were observed. These holes were residues of Ni silicides that had been etched away by the silicide-etching solution. The Ni residues in CF-MIC were much lower than those in conventional MIC. This reduction must be due to the introduction of chemical oxide layer in CF-MIC processes. Oxide filter layer can avoid Ni directly contact with α-Si and remove unreacted Ni easily from surface.
Fig. 2-5 SEM images of the silicide etching holes of MIC and CF-MIC poly-Si films.
Secondary-ion mass spectroscopy (SIMS) depth profile was also used to analyze the Ni concentrations (residues) in Si films (without silicide-etching process). As expected, Ni content in CF-MIC was much less than that in MIC as shown in Fig. 2-6. Obviously, chemical oxide layer can reduce the Ni concentrations in Si films. This is because the diffusivity of Ni in α-Si is 108 times higher than that in SiO2 at 500oC [61]-[62]. As a result, chemical oxide serves as a filter, which can retard the in-diffusion of Ni into Si films. In other words, Ni concentrations in Si films were reduced.
Fig. 2-6 SIMS depth profiles of nickel in the structure of MIC and CF-MIC poly-Si films.
Moreover, to investigate the Ni reduction in various thicknesses of chemical oxide layer, a relation of Ni intensity at a depth of 50 nm versus immersed time after MIC process is shown in Fig. 2-7. It conformed to the basic diffusion model to presented exponential decay as a function of immersed time and saturated at a minimum of Ni intensity after dipped for 10 min. The result indicated that the chemical oxide introduced between α-Si layer and Ni layer can greatly reduced Ni concentration in MIC TFTs depended on thickness of the chemical oxide. Hence the leakage current was improved to an optimum with the reduction of Ni concentration because of increased thickness of chemical oxide.
Fig. 2-7 A relation of Ni intensity at a depth of 50 nm versus immersed time by SIMS after MIC annealing.
2.3.3 Surface roughness of MIC poly-Si films after crystallization
After Ni film and chemical oxidewere removed, their surfaces (without silicide-etching) were measured using atomic force microscopy (AFM) to identify the degree of texturing. As shown in Fig. 2-8, the root mean square surface (rms) roughness of CF-MIC surface (0.798 nm) was less than that of CF-MIC surface (1.348 nm). These results are in agreement with the MICC studies of Choi et al. [56], who found that MIC with cap layer can achieve a clean and smooth surface.
Fig. 2-8 surface roughness of MIC and CF-MIC poly-Si films
2.3.4 Electrical performance of MIC and CF-MIC TFTs
Figure 2-9 exhibits the ID–VG transfer characteristics of TFTs at a drain bias of 5 V. The device parameters were extracted at W/L = 10/10 μm, and ten TFTs were measured. The average values with standard deviations in parentheses were shown in Table 2-1. The threshold voltage (Vth) is defined at a normalized drain current of IDS = (W/L) × 100nA at VDS
= 5V. The field-effect mobility (µFE) is extracted from the maximum value of transconductance at VDS = 0.1V. As shown in Table 2-1, the electrical characters of CF-MIC TFTs were significantly improved. This improvement must be due to the introduction of chemical oxide layer in CF-MIC processes. Compared with conventional MIC TFTs, CF-MIC TFTs shows a 17.3-fold increase in the on/off current ratio and a 14.3-fold decrease in the minimum leakage current.
Fig. 2-9 Typical IDS-VGS transfer characteristics and filed-effect mobility of of MIC, CF-MIC and SPC TFTs (W / L = 10 / 10 μm)
Table 2-1 Average device characteristics of MIC, CF-MIC and SPC TFTs with standard deviations in parentheses
The leakage current improvement was attributed to the reduction of Ni concentration in the CF-MIC films. It is known that Ni-related defects might degrade electric performance because the trap states introduced dangling bonds and strain bonds [63]. The chemical oxide layer reduced content of Ni (Ni-related defect) into channel layer during MIC annealing process. With the reduction of the Ni concentration, the minimum leakage current was reduced and therefore the on/off current ratio was increased [64]-[65]. In addition, the carrier mobility also increased due to lower impurity scattering of Ni-related defects and grain boundaries. However, the Vth of CF-MIC was showed a positive shift compared with conventional MIC. The result is similar to earlier findings suggesting that the negative shift of Vth was caused by positive charge in high Ni residues poly-Si film [54].
The electrical performances of SPC TFTs were also measured. As shown in Table 2-1, Fig. 2-9, the on/off current ratio of CF-MIC TFTs was higher than that of SPC TFTs. The leakage current of CF-MIC TFTs was as low that of SPC TFTs. This also demonstrated the reduction of Ni residues through the introduction of chemical oxide layer.
2.3.5 Influence of grain size on field-effect mobility
In general, the grains of MIC were crystallized from top to down and formed needle-like MIC grains [66]. Figure 2-10 shows the plane-view images of transmission electronic
approximately 8~10 nm and 15~18 nm, respectively. The variation of grain size was attributed to the different Ni concentration during MIC annealing process [67]. The amount of nucleation site of NiSi2 in MIC is higher than that in CF-MIC due to higher Ni concentration.
Therefore, the grain size of MIC was less than that of CF-MIC.
In the MIC poly-Si films, dangling bonds in grain boundaries serve as the trapping centers, which trap many free carriers (either electrons or holes) and consequently hinder carriers from conduction [33]-[35]. For this reason, the field-effect mobility increased from 25.5 to 35.8 cm2 V-1 S-1 owning to the larger grain size in CF-MIC.
Fig. 2-10 The plane-view images of transmission electronic microscopy (TEM) of MIC and CF-MIC poly-Si films.
2.4 Summary
The chemical oxide filter layer was introduced into MIC processes to reduce the leakage current of MIC TFTs. The process was very simple and without extra expensive instrument. It just added α-Si coated sample into chemical solution before depositing the Ni film. The chemical oxide growth controlled by diffusion of reactants through the pre-existing layer conformed to the model of oxide growth and there is a saturation thickness of 3.4 nm after dipped for 10 min. It was also found that it conformed to the basic diffusion model to presented exponential decay as a function of immersed time and saturated at a minimum of Ni concentration after dipped for 10 min.
As the results, the electrical performance of MIC TFTs with chemical oxide layer was significantly improved, including in higher field-effect mobility, superior subthreshold slope, and higher on/off current ratio. Compared with conventional MIC TFTs, CF-MIC TFTs shows a 14.3-fold decrease in the minimum leakage current and a 17.3-fold increase in the on/off current ratio. This is because the chemical oxide layer can avoid Ni directly contact with α-Si, avoid excess of Ni atoms into α-Si layer and remove unreacted Ni easily from surface.
Chapter 3
Effect of Nickel Concentration on Electrical Characteristics of MIC TFTs: Source/Drain Series
Resistance, Bias Reliability and Thermal Stability
3.1 Introduction
In recent years, low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been widely applied to high resolution integrated active-matrix organic light-emitting diodes (AMOLED), which exhibit good electrical properties and can be used in the realization of glass substrate [48]. In various fabrication for LTPS, metal-induced crystallization (MIC) is promising for use owing to its low cost, good uniformity, low crystallization temperature (~500 ) and short crystallization time (0.5 ℃ - 5 h) [50]-[51].
Unfortunately, Ni and NiSi2 residues in the poly-Si film increases the leakage current and shifts the threshold voltage [52]-[53]. In chapter 2, the leakage current has been significantly reduced by decreasing the Ni concentration through use of a chemical oxide filter layer (CF-MIC).
Noteworthily, while most studies have focused only on reducing Ni contamination to improve the leakage current, lowering the Ni concentration may change the source/drain (S/D)
series resistance of MIC TFTs. Inevitably, the S/D series resistance negatively influences on the device performance, especially on-state current and mobility [68]-[70]. This phenomenon becomes seriously due to increased ratio of the S/D series resistance at short channel devices.
Therefore, improving the performance of MIC TFTs requires understanding in detail how the Ni concentration affects S/D series resistance. However, to our knowledge, exactly how Ni concentration and series resistance are related at the S/D region has not been examined. In the part 1, the S/D series resistance of MIC TFTs was investigated by using transmission line method [69].
Moreover, bias reliability and thermal stability became major concerns for AMOLED display applications, especially when devices are operated under hot carrier condition and high temperature environment. It is known that hot carrier stress under high gate and high drain voltages decreases on-state current and increases the threshold voltage (Vth) [71]-[72].
Furthermore, devices in high temperature environment show a poor thermal stability leading to large leakage current and shifts Vth [73]-[74]. Although reducing Ni concentration is an effective way to improve leakage current, the Ni concentration effect on bias reliability and thermal stability was also important for AMOLED display application. It is interesting how the reduction of Ni concentration affect the bias reliability and thermal stability of MIC TFTs.
In the part 2, the effect of Ni concentration on bias reliability and thermal stability were investigated, which were reflected the behavior at on-state and off-state region, respectively.
In this study, exactly how the Ni concentration affects these electrical characteristics of MIC TFTs is examined by using the conventional MIC and CF-MIC to represent high and low Ni concentration devices, respectively. Results of this study demonstrate that the S/D
In this study, exactly how the Ni concentration affects these electrical characteristics of MIC TFTs is examined by using the conventional MIC and CF-MIC to represent high and low Ni concentration devices, respectively. Results of this study demonstrate that the S/D