Motivation

For non-planar devices like FinFET, it is becoming more difficult to achieve uniform S/D doping by using implantation on account of shadowing effects caused by tightened pitch with each technology node [23]. Meanwhile, S/D regions for the cell device contained in a high-density 3D memory technology such as BiCS [24] are formed by gate fringing fields from neighboring cells, which are hard to manipulate and may easily result in degradation of read current. In line with this, recently much attention has been paid to the device without junction [25]. In other words, S/D and channel have the same type of doping and the device operates in the AcM.

Our group previously introduced a poly-Si NW transistor with rectangular-shaped NW channels and two independent gates [26]. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. More than this, when the channel thickness is thin enough, the gate-coupling effect with the double gates could occur and enhance the gate controllability on the channel, improving the electrical characteristics like on-current and

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subthreshold swing (SS) [27]. Because of these advantages, we tried to apply the double-gated configuration to the AcM device. In this study, we fabricated the p-type AcM double-gated device with a high doping concentration in the channel, expecting to obtain better electrical characteristics via the effective controllability by the double gates. A comparison in device characteristics between the devices with the conventional ones with undoped channels is also made in this study.

1.4 Organization of the Thesis

In Chapter 2, we present the fabrication of the p-type AcM double-gate TFT, and the basic process flow will be briefly described. The measurement setups are also presented in this chapter.

In Chapter 3, we present and discuss the electrical characteristics of the fabricated devices, which include the on-current, SS and SCE. The results of the two single-gated (SG) modes and the double-gated (DG) mode will be discussed respectively. Also, we compare the electrical characteristics with the conventional device.

Finally, we summarize the conclusion from our experimental results and suggest future work in Chapter 4.

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Chapter 2

Device Fabrication and Measurement

Setup

2.1 Device Fabrication and Process Flow

In this section, we introduce the basic process flow of the p-type AcM double-gated device. Figure 2.1 shows the schematic process flow of the proposed device. First, a 60 nm-thick SiN layer was deposited on a Si wafer capped with a 100 nm-thick thermal oxide. Because of the p-type doping of the channels, the AcM device prefers a gate material with a low work function such as n⁺ polycrystalline silicon in order to achieve a suitable threshold voltage (Vth) (that is, not too positive for p-type device). Therefore, a 100 nm-thick in-situ doped n⁺ poly-Si and 50 nm-thick SiN were deposited sequentially to serve as the 1st gate stack. After the gate stack patterning (Fig. 2.1(a)), a plasma etching with high selectivity to SiN was used for lateral etching of the n⁺ poly-Si (Fig. 2.1(b)). Then 10 nm-thick TEOS oxide and 100 nm-thick amorphous Si were deposited, which subsequently underwent 600^oC annealing in N2 ambient for 24 hours (Fig. 2.1(c)).

After P⁺ doping using BF2+

at a dose of 5 × 10¹⁴ cm^-2 (Fig. 2.1(d)), samples were annealed in nitrogen ambient at 900^oC for 30 min to drive the dopants into the NW channels (Fig. 2.1(e)). To avoid large S/D resistance, an additional S/D doping was performed by implanting BF2+

at a dose of 5 × 10¹⁵ cm^-2 (Fig. 2.1(f)).

Next, the channel and S/D regions were defined by reactive plasma etching (Fig.

2.1(g)). The 2nd gate electrode comprising of 10 nm-thick TEOS oxide and 100

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nm-thick in-situ doped n⁺ poly-Si was then deposited followed by patterning (Fig.

2.1(h)). A 200 nm-thick oxide was subsequently deposited as passivation layer.

The device was completed after standard metallization steps. For the IM device with undoped channels, the fabrication flow is similar to what was described above except that steps in Fig. 2.1(d) and Fig. 2.1(e) are omitted.

The layout of the double-gated device is shown in Fig. 2.2(a). Fig. 2.2(b) is a cross-sectional view of the device along line in Fig. 2.2(a). It can be seen that the 1st gate is surrounded by the SiN layers and two rectangular NW channels.

2.2 Images of Fabricated Devices

In Chapter 3 we will discuss the electrical characteristics of the fabricated devices including the AcM and the IM devices. However, for the AcM device, its fabrication contained additional channel implant and drive-in steps for driving the dopants into the NW channels, as shown in Fig. 2.1(d) and Fig. 2.1(e). Hence it is imperative to check the texture and grain size of the fabricated NW channels to see if there exists any physical difference between the two devices. Such information is useful for us to compare their electrical characteristics more objectively.

The cross-sectional transmission electron microscope (TEM) images for the fabricated devices are given in Fig. 2.3, from which the rectangular NW channels can be observed. It can be seen that the channel thickness is about 20nm for the IM device and 23nm for the AcM device. From these TEM images, it can be seen that the channel thicknesses for the two devices are roughly the same, though a little thicker for the AcM device.

Due to the high temperature drive-in steps for the AcM device, the grain

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size in NW channels may become larger. However, prior to the above steps, the AcM device had undergone a 600^oC annealing in N2 ambient for 24 hours to transform the amorphous Si into polycrystalline state, and the grain size for the AcM device may not increase dramatically. This is conformed with the scanning electron microscope (SEM) images of the two types of poly-Si films shown in Figs.

2.4(a) and (b). As can be seen in the figures, the grain sizes for the poly-Si films are similar. Actually the grain size for the AcM device is even slightly smaller than that for the IM device. This phenomenon may be due to the diffusion of high doping concentration of BF2+

[28]. In conclusion, we can approximately regard the grain sizes for both devices as the same.

2.3 Measurement Setup

In our study, electrical measurements of all devices were evaluated by an HP4156A precision semiconductor parameter analyzer, and the measurement temperature was maintained at 25^oC.

The basic electrical parameters of the fabricated device were extracted from the electrical characteristics. By the way, the Vth was not extrapolated from the Id-Vg curves. Due to the contribution of body conduction for the AcM device, its operation is different from that of the IM device and the extrapolation technique could be inaccurate [29]. Instead, it is suitable to define the Vth for a fixed drain current level. The surface potential (ΦS) criterion can be set to zero for the AcM device [30]. For our experiment, the Vth was defined as the value of Vg when Id

equals 10nA × under Vd of 0.5V, where W and L are the channel width and the channel length, respectively. For the channel width W, the value was estimated from the TEM images shown in Figs. 2.3(a) and (b) for the IM and

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AcM devices, respectively. The SS is calculated by the following equation:

= ^{( )} , (Eq. 2-1) and for both AcM and IM devices, the minimum value in the subthreshold swing is extracted. The transconductance (Gm) was also extracted from the Id-Vg curves, and for on-current (Ion), the value was defined as the Id when Vg–Vth = -3V.

For our double-gated structure, the operation modes of measurements are described as below: SG-1 and SG-2 modes denote the scheme when the 1st or 2nd gate serves as the driving gate while the other gate electrode is grounded. In DG mode, both gates are connected together to serve as the driving gate.

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Chapter 3

Results and Discussion

3.1 Basic Electrical Characteristics 3.1.1 Transfer Curves

Figure 3.1 shows the transfer curves of an IM device. Due to the existence of un-gated regions which contribute extra parasitic resistances in the SG-1 mode [31], the electrical performance of the SG-1 mode is basically worse than that of the SG-2 mode. For the IM devices, the drain current conducts when the inversion layer is formed near the interface between the channel and gate dielectric. From the plot, we can see the drain currents in the three operation modes rise up at almost the same gate voltage. From the TEM images in Chapter 2, the channel thickness for our fabricated device is quite thin (down to about 20nm), and hence the gate coupling effect [32] is pretty strong so that the gate controllability and electrical performance are obviously enhanced in the DG mode [26]. As is evident in the current-drive of a single device, the Ion of the DG mode is larger than the sum of those of the two SG modes. Also, owing to the effect of volume-inversion on account of the thin channel thickness [33], the SS under the DG mode is better than that in the SG mode.

The transfer curves of the AcM device are given in Fig. 3.2. There are some differences in electrical characteristics from those of the IM device. First, it can be seen that the curves of the AcM device apparently shift to the right (more positive value of Vth), showing the normally-on characteristics. Moreover, due to

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the different conduction mechanisms for the AcM devices [34], the characteristics of Id-Vg curves are different from those of the IM devices. In the AcM case, the key point is whether the device can be effectively turned off. When the AcM device is turned on, the channel flowed through by the carriers contained in the accumulation region at the surface and the quasi-neutral region in the film center. On the other hand, for the PMOS devices, if the gate bias isn’t sufficiently positive to deplete the free holes in the channel, a high leakage current will flow and the device cannot be effectively turned off. Thanks to the ultra-thin channel thickness in our fabricated devices, the AcM device can still be successfully turned off in all operation modes despite the very high channel doping (>10¹⁸/cm^-3). Moreover, for the 0.7µm channel length, the drain-to-source leakage current in each operation modes is significantly larger than that for the device with 2µm channel length. It may be due the severe SCE and the large bulk leakage current for the AcM devices, which will be discussed in the next section.

For the AcM devices, the gate coupling effect is also obvious under the DG mode. However, its influence is quite different from that of the IM device. For the DG mode, the two gates are simultaneously used to deplete the channel and can therefore more effectively turn off the device, leading to a smaller SS and a smaller Vth.

Figure 3.3 shows the threshold voltage (Vth) of the three operation modes for the two types of devices with 0.7µm channel length. For the IM devices, the conduction is through inversion carriers induced near the channel interface by the gate bias. The Vth is more positive for the DG mode than the SG-2 mode and SG-1 mode, indicating the IM device can be more effectively switched with the switching mode [27]. However, for the AcM device, the device is normally on and its switching depends on the ability of depleting the carriers in the body. As

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shown in Fig. 3.3, the order in the magnitude of Vth among various modes for the AcM device is opposite to that of the IM one, and the Vth of the DG mode, which has the strongest gate controllability over the channel, is the smallest. This is reasonable since the DG mode depletes the channel from the two opposite channel interfaces and the two depletion regions would merge at around the center of the channel as the device is turned off. For the SG modes, the depletion starts from only one of the two channel interfaces where the driving bias is applied and it needs to deplete the whole channel for effectively switching off the device, thus the SS is worse while the Vth is larger.

Figure 3.4 shows the Ion characteristics as a function of channel length for both devices. In the AcM devices, the carriers flow through the whole channel, thus their current level is significantly larger than that of the IM ones in which the conduction is mainly through the channel interface. For the two types of devices, the current of SG-1 mode is smaller than that of SG-2 mode. As explained in [31], the current path of the SG-1 mode contains un-gated regions, as shown in Fig. 3.5, which drastically increase the series resistance. Regarding this problem which leads to the degraded performance, the Ion of the SG-1 mode is obviously lower than that of the SG-2 mode for the IM devices, and under the DG mode, the Ion is almost dominated by that of the SG-2 mode. This issue is slightly ameliorated when adopting the AcM scheme, and due to the high doping concentration in the channel, impact of the un-gated regions is relieved, as evidenced by the smaller difference in Ion between the two SG modes.

3.1.2 Output Characteristics

Figure 3.6 shows the output characteristics for both devices. For the AcM devices, the current conduction occurs through the whole channel layer rather

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than the surface, and it is apparent that the output current is enhanced significantly for the AcM devices, which can provide about 328% enhancement of saturation current at Vg-Vth = -4V and VD = -5V for the 2µm channel length, and 198% enhancement for the 0.7µm channel length over the IM devices.

The S/D resistance can be extracted from the Id-Vg curves in Fig. 3.6 by using the linear regression method. Fig. 3.7 shows the total resistance (Rtot, = ) as a function of channel length. The S/D resistance can be extracted from the intercept of y-axis of the plots. Because we had performed an extra implantation on the AcM devices to reduce the S/D resistance [35], the extracted S/D resistances are almost the same for the two devices. The value of the AcM devices is about 12.4kΩ, just a little smaller than 13.8kΩ of the IM devices, presumably due to the lower-resistivity path in the AcM device between the channel and the S/D as explained in [36]. The channel resistance can be obtained by extracting the S/D resistance from the Rtot, and the results for both devices are shown in Fig.

3.8. Due to the high channel doping for the AcM devices, the channel resistance is much smaller than that for the IM devices with undoped channel. For the long channel length, the difference of channel resistance between the two devices is more obvious, and the difference diminishes with decreasing channel length. The outcome is consistent with the results shown in Fig. 3.6 that the enhancement of the output characteristics is more prominent for the long-channel device.

3.1.3 Simulation Results

Here we use the TCAD simulation to analyze the differences in conduction mechanisms between the two types of devices in the subthreshold region. The simulated structures have a uniform doping concentration in the channel and S/D regions for the AcM devices. The channel has boron doping at a

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concentration of 5 × 10¹⁸ cm^-3, and the channel thickness is 20nm while the gate oxide thickness is 10nm. The work function of gate electrode is 4.15eV, and here we ignore the quantum effect to simplify the condition. The Vth is defined as the value of Vg when Id equals 10nA. Figure 3.9 shows the simulation results along the channel depth for the IM devices. As the absolute value of gate overdrive increases in Fig 3.9(a), the energy bands near the interfaces gradually bend and invert the surface region. Then we can see from Fig. 3.9(b) that the concentration of the inverted holes induced near the two interfaces increases with increasing gate overdrive.

The simulation results for the AcM device are shown in Fig. 3.10. In Fig 3.10(a), when the absolute value of gate overdrive increases, the surface bend bending is relieved while the width of a flat-band region (zero electric field) in the central Si channel increases with increasing gate overdrive. It can be noted from Fig. 3.10(b) that the carriers are concentrated at the center of the Si bulk [37]. Unlike the IM device whose channel body is nearly depleted when the device is turned on, the quasi-neutral region of the AcM device gradually expands from the channel center to the interfaces with increasing gate overdrive.

In conclusion, from the simulation results, we can define the differences of conduction mechanisms between the two devices. For the IM devices, the conduction carriers are from the surface charges induced by the gate bias, and for the AcM devices with doped channel, the conduction is mainly through the center of the Si bulk opened by the gate bias.

3.2 Subthreshold Characteristics

3.2.1 Short Channel Effects

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The SS characteristics as a function of channel length for both devices are given in Fig. 3.11. For the AcM devices, both SG modes start to exhibit obvious rise in SS when the channel length is smaller than 1m. Such phenomenon is relaxed with the DG mode, indicating it has the highest immunity to SCEs among the three modes. Moreover, it is interesting to note that when the channel length is larger than 1m, the SS in the DG mode for the AcM devices is better than that for the IM ones. However, the overall SS degradation with decreasing channel length is still more severe for the AcM devices. The Vth as a function of channel length is given in Fig. 3.12. It can be seen that the values of Vth for the AcM devices are all positive, exhibiting the feature of normally-on transistor.

However, for the AcM devices, the Vth roll-off is still more severe, and, with channel length of 0.4m, Vth as high as 2.3V is recorded.

As mentioned above, both SS degradation and Vth roll-off are severer for the AcM devices, which seem to have worse SCEs than the IM devices, and such phenomenon can be explained from the perspective of the difference in effective oxide thickness (EOT) between the two types of devices. Fig. 3.13 is the schematic illustration of current paths under DG mode of operation for the two types of devices. For the IM devices, the current is mainly conducted along the inversion layer induced near the interfaces and the EOT is approximately equal to the physical oxide thickness. However, for the AcM devices, because the current path in the subthreshold region is mainly along the central Si channel, the physical distance between the gate and the channel is larger than the case of the IM. In other words, there is an additional gate dielectric contributed by the Si depletion layer, resulting in an increase in the EOT of the devices. Moreover, this additional gate dielectric layer not only exhibits in the AcM devices, but also depends on the gate bias. Here we use the TCAD simulation to explain such

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situation for the AcM devices with the simulated structures described in the last section, and we use the SG mode to demonstrate in the following simulation.

situation for the AcM devices with the simulated structures described in the last section, and we use the SG mode to demonstrate in the following simulation.